參數(shù)資料
型號: MC68HC05P18MDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 91/144頁
文件大?。?/td> 1348K
代理商: MC68HC05P18MDW
Advance Information
MC68HC(8)05P18 — Rev. 2.0
50
Resets
MOTOROLA
Resets
Figure 5-1. Reset Block Diagram
5.4 Internal Resets
The three internally generated resets are:
Initial power-on reset (POR)
Computer operating properly (COP) watchdog timer
Low-voltage reset (LVR) functions
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
The POR will generate the RST signal and reset the MCU. The POR will
also pull the RESET pin low at the same time, allowing external devices
to be reset with the MCU. If any other reset function is active at the end
CPU
LATCH
RESET
COP WATCHDOG
(COPR)
RST
OSC
DATA
ADDRESS
PH2
TO OTHER
PERIPHERALS
S
LOW-VOLTAGE
RESET (LVR)
VDD
IRQ
MODE
SELECT
TO IRQ
LOGIC
LATCH
R
POWER-ON RESET
(POR)
VDD
PH2
CLOCKED
ONE-SHOT
(PULSE WIDTH = 4 x E-CLK)
D
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