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參數(shù)資料
| 型號(hào)： | MC68HC05P18MDW |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 86/144頁(yè) |
| 文件大小： | 1348K |
| 代理商： | MC68HC05P18MDW |
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Advance Information
MC68HC(8)05P18 — Rev. 2.0
46
Interrupts
MOTOROLA
Interrupts
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level
2. Falling edge on any enabled port A interrupt pin with all other
enabled port A interrupt pins and the IRQ pin at a high level
If level sensitivity is chosen, the active high state of the IRQ input can
also activate an IRQ request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the:
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level
3. Low level on any enabled port A interrupt pin
4. Falling edge on any enabled port A interrupt pin with all enabled
port A interrupt pins and the IRQ pin at a high level
This interrupt is serviced by the interrupt service routine located at the
address specified by the contents of $3FFA and $3FFB. The IRQ latch
is cleared automatically by entering the interrupt service routine.
4.3.3.2 Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0–PA7 port
pins if enabled by individual mask options. With pullup enabled, each
port A pin can activate the IRQ interrupt function and the interrupt
operation will be the same as for inputs to the IRQ pin. Once enabled by
mask option, each individual port A pin can be disabled as an interrupt
source if its corresponding DDR bit is configured for output mode.
NOTE:
The BIH and BIL instructions apply to the output of the logic OR function
of the enabled PA0–PA7 interrupt pins and the IRQ pin. The BIH and BIL
instructions do not test only the state of the IRQ pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68HC05P1A | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1ADW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1AP | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1CDW | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P1CP | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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