Resets and Interrupts
MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet, Rev. 5.0
140
Freescale Semiconductor
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR since any reset
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR since any reset
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR since any reset
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by forced monitor mode entry.
0 = POR or read of SRSR since any reset
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR since any reset
13.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
13.3.1 Effects
An interrupt:
Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
Loads the program counter with a user-defined vector address
Address:
$FE01
Bit 7
POR
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 13-3. SIM Reset Status Register (SRSR)