Functional Description
MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
159
Slow Data Tolerance
Figure 14-8
shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
Figure 14-8. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times
×
16 RT cycles
+ 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
Figure 14-8
, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 9 bit times
×
16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is:
147
–
154
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times
×
16 RT cycles
+ 10 RT cycles = 170 RT cycles.
With the misaligned character shown in
Figure 14-8
, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 10 bit times
×
16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
163
–
170
Fast Data Tolerance
Figure 14-9
shows how much a fast received character can be misaligned without causing a noise error
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
Figure 14-9. Fast Data
MSB
STOP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DATA SAMPLES
RECEIVER
RT CLOCK
154
100
×
4.54%
=
170
100
×
4.12%
=
IDLE OR NEXT CHARACTER
STOP
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DATA SAMPLE
RECEIVER
RT CLOCK