M
7
F
C
Table 6-2. Opcode Map
Read-Modify-Write
INH
IX1
SP1
Bit Manipulation
DIR
Branch
REL
Control
INH
Register/Memory
IX2
DIR
DIR
INH
IX
INH
IMM
DIR
EXT
SP2
IX1
SP1
IX
0
1
2
3
4
5
6
9E6
7
8
9
A
B
C
D
9ED
E
9EE
F
0
5
BRSET0
3
DIR
5
4
BSET0
2
DIR
4
3
BRA
2
REL
3
4
NEG
DIR
5
CBEQ
3
2
1
NEGA
1
INH
4
1
NEGX
1
INH
4
4
NEG
2
IX1
5
5
NEG
SP1
6
CBEQ
4
3
3
NEG
1
IX
4
7
RTI
INH
4
RTS
INH
1
3
BGE
2
REL
3
BLT
REL
3
BGT
REL
3
BLE
REL
2
TXS
INH
2
TSX
INH
2
SUB
2
IMM
2
3
SUB
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
AND
DIR
3
BIT
DIR
3
LDA
DIR
3
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
4
JSR
DIR
3
LDX
DIR
3
STX
DIR
2
4
SUB
3
EXT
4
4
SUB
3
IX2
4
5
SUB
SP2
5
CMP
SP2
5
SBC
SP2
5
CPX
SP2
5
AND
SP2
5
BIT
SP2
5
LDA
SP2
5
STA
SP2
5
EOR
SP2
5
ADC
SP2
5
ORA
SP2
5
ADD
SP2
4
3
SUB
2
IX1
3
4
SUB
3
SP1
4
2
SUB
1
IX
2
1
BRCLR0
3
DIR
BCLR0
2
DIR
4
BRN
2
REL
3
BHI
REL
3
BLS
REL
3
BCC
REL
3
BCS
REL
3
BNE
REL
3
BEQ
REL
3
BHCC
2
DIR
CBEQA
3
IMM
5
CBEQX
3
IMM
7
DIV
INH
1
COMX
1
CBEQ
3 IX1+
SP1
CBEQ
2
IX+
1
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
LDA
IMM
2
AIS
IMM
2
EOR
IMM
2
ADC
IMM
2
ORA
IMM
2
ADD
IMM
2
2
CMP
3
EXT
4
CMP
IX2
4
SBC
IX2
4
CPX
IX2
4
AND
IX2
4
BIT
IX2
4
LDA
IX2
4
STA
IX2
3
4
CMP
2
IX1
3
CMP
SP1
4
SBC
SP1
4
CPX
SP1
4
AND
SP1
4
BIT
SP1
4
LDA
SP1
4
STA
SP1
4
EOR
SP1
4
ADC
SP1
4
ORA
SP1
4
ADD
SP1
3
CMP
1
IX
2
2
5
BRSET1
3
DIR
5
BSET1
2
DIR
4
2
MUL
1
INH
1
1
3
NSA
1
INH
4
DAA
1
INH
3
2
2
2
SBC
3
EXT
4
3
4
SBC
2
IX1
3
3
SBC
1
IX
2
3
BRCLR1
3
DIR
BCLR1
2
DIR
4
2
4
COM
2
DIR
4
COMA
1
INH
1
INH
1
COM
2
IX1
4
5
COM
SP1
5
LSR
SP1
3
COM
1
IX
3
9
SWI
INH
2
TAP
INH
1
TPA
INH
2
PULA
INH
2
PSHA
INH
1
2
2
2
CPX
3
EXT
4
3
4
CPX
2
IX1
3
3
CPX
1
IX
2
4
5
BRSET2
3
DIR
5
BSET2
2
DIR
4
2
LSR
2
DIR
4
LSRA
INH
3
LDHX
IMM
1
RORA
1
1
LSRX
1
INH
4
LSR
2
IX1
3
3
LSR
1
IX
4
1
1
2
2
AND
3
EXT
4
BIT
EXT
4
LDA
EXT
4
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
5
JSR
EXT
4
LDX
EXT
4
STX
EXT
3
4
AND
2
IX1
3
3
AND
1
IX
2
5
BRCLR2
3
DIR
BCLR2
2
DIR
4
2
STHX
DIR
2
3
LDHX
2
DIR
1
CPHX
3
IMM
4
CPHX
2
DIR
3
1
1
2
2
3
3
4
BIT
2
IX1
3
3
BIT
1
IX
2
6
5
BRSET3
3
DIR
5
BSET3
2
DIR
4
2
4
ROR
2
DIR
4
INH
1
RORX
1
INH
1
ROR
2
IX1
4
5
ROR
SP1
5
ASR
SP1
5
LSL
SP1
5
ROL
SP1
5
DEC
SP1
6
DBNZ
SP1
5
INC
SP1
4
TST
SP1
3
ROR
1
IX
3
1
2
2
3
3
4
LDA
2
IX1
3
3
LDA
1
IX
2
7
BRCLR3
3
DIR
BCLR3
2
DIR
4
2
ASR
2
DIR
4
ASRA
INH
1
ASRX
1
INH
1
ASR
2
IX1
4
3
ASR
1
IX
3
1
1
TAX
1
INH
1
2
2
3
3
4
STA
2
IX1
3
3
STA
1
IX
2
8
5
BRSET4
3
DIR
5
BSET4
2
DIR
4
REL
3
LSL
2
DIR
4
1
LSLA
INH
1
ROLA
INH
1
LSLX
1
INH
1
LSL
2
IX1
4
3
LSL
1
IX
3
2
PULX
INH
2
PSHX
INH
1
CLC
1
INH
1
2
2
3
4
EOR
3
IX2
4
4
EOR
2
IX1
3
3
EOR
1
IX
2
9
BRCLR4
3
DIR
BCLR4
2
DIR
4
BHCS
2
REL
3
BPL
REL
3
BMI
REL
3
BMC
REL
3
BMS
REL
3
BIL
REL
3
BIH
REL
ROL
2
DIR
4
1
ROLX
1
INH
1
ROL
2
IX1
4
3
ROL
1
IX
3
1
SEC
1
INH
2
CLI
INH
2
SEI
INH
1
RSP
INH
1
NOP
INH
2
2
3
ADC
3
IX2
4
4
ADC
2
IX1
3
3
ADC
1
IX
2
A
5
BRSET5
3
DIR
5
BSET5
2
DIR
4
2
DEC
2
DIR
5
1
DECA
INH
1
DECX
1
INH
3
DEC
2
IX1
5
3
DEC
1
IX
4
2
PULH
1
INH
2
1
2
2
3
ORA
IX2
4
ADD
IX2
4
JMP
IX2
6
JSR
IX2
4
LDX
IX2
4
STX
IX2
3
4
ORA
2
IX1
3
3
ORA
1
IX
2
B
BRCLR5
3
DIR
BCLR5
2
DIR
4
2
DBNZ
3
DIR
4
3
DBNZA
2
INH
1
DBNZX
2
INH
1
DBNZ
3
IX1
4
4
DBNZ
2
IX
3
PSHH
1
INH
1
1
2
2
3
3
4
ADD
2
IX1
3
3
ADD
1
IX
2
C
5
BRSET6
3
DIR
5
BSET6
2
DIR
4
2
INC
2
DIR
3
INCA
INH
1
TSTA
INH
5
MOV
DD
1
CLRA
INH
1
INCX
1
INH
1
INC
2
IX1
3
3
INC
1
IX
2
CLRH
INH
1
1
2
3
3
JMP
2
IX1
5
JMP
1
IX
4
D
BRCLR6
3
DIR
BCLR6
2
DIR
4
2
TST
2
DIR
1
TSTX
1
INH
4
TST
2
IX1
4
3
TST
1
IX
4
1
4
BSR
2
REL
2
LDX
IMM
2
AIX
IMM
2
3
3
JSR
2
IX1
3
JSR
1
IX
2
E
5
BRSET7
3
DIR
5
BSET7
2
DIR
4
2
3
MOV
2 DIX+
MOV
3
IMD
3
MOV
2 IX+D
1
STOP
INH
1
*
2
2
3
3
5
LDX
SP2
5
STX
SP2
4
LDX
2
IX1
3
4
LDX
SP1
4
STX
SP1
3
LDX
1
IX
2
F
BRCLR7
3
DIR
BCLR7
2
DIR
2
3
CLR
2
DIR
1
1
CLRX
1
INH
CLR
2
IX1
4
CLR
SP1
3
2
CLR
1
IX
1
WAIT
1
INH
1
TXA
1
INH
2
2
3
3
4
STX
2
IX1
3
STX
1
IX
INH Inherent
IMM Immediate
DIR Direct
EXT Extended
DD
Direct-Direct
IX+D Indexed-Direct
*
Pre-byte for stack pointer indexed instructions
REL Relative
IX
Indexed, No Offset
IX1
Indexed, 8-Bit Offset
IX2
Indexed, 16-Bit Offset
IMD Immediate-Direct
DIX+ Direct-Indexed
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+
Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5
BRSET0
3
DIR
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
MSB
LSB
MSB
LSB