
MOTOROLA
6-8
CENTRAL PROCESSING UNIT
M68HC11
REFERENCE MANUAL
6.2.3 Direct (DIR)
In the direct addressing mode, the least significant byte of the effective address of the
instruction appears in the byte following the opcode. The high-order byte of the effec-
tive address is assumed to be $00 and is not included as an instruction byte (saves
program memory space and execution time). This fact limits the use of direct address-
ing mode to operands in the $0000–$00FF area of memory (called the direct page).
The direct addressing mode is sometimes called zero-page addressing mode. The
length of most instructions using the direct addressing mode is two bytes: one for the
opcode and one for the effective address. Instructions from the second, third, and
fourth opcode-map pages require a page-select prebyte prior to the opcode byte. Only
four direct addressing mode instructions involving index register Y require this extra
prebyte.
Direct addressing allows the user to access $0000–$00FF, using instructions that take
one less byte of program memory space than the equivalent instructions using extend-
ed addressing. By eliminating the additional memory access, execution time is re-
duced by one cycle. In the course of a large program, this savings can be substantial.
For most applications, the default memory map of the microcontroller unit (MCU),
which places internal random-access memory (RAM) in the $0000–$00FF area, is a
good choice because the designer can assign these locations to frequently referenced
data variables. In some MCU applications, it is desirable to locate the internal registers
in this premium memory space. This arrangement might be desirable in an I/O-inten-
sive application in which the program space savings are important or in the case of
some very critical timing requirement in which the extra cycle for extended addressing
mode is undesirable. In the M68HC11 MCU, software can configure the memory map
so that internal RAM, and/or internal registers, or external memory space can occupy
these addresses (see
3.3.1 RAM and I/O Mapping Register (INIT)
.
There are some instructions that provide for extended addressing mode but not direct
addressing mode. These instructions, which are members of a group called read-mod-
ify-write instructions, operate directly on memory (opcodes $40–$7F except jump
(JMP) and test for zero or minus (TST) on all opcode pages) and have the following
form:
<operation>M
M
The increment memory byte (INC), decrement memory byte (DEC), clear memory
byte (CLR), and one’s complement memory byte (COM) instructions are members of
this group, and each supports extended addressing mode but not direct addressing
mode. The following example shows the direct and extended addressing modes.
Machine Code
B3 00 12
Label
Operation
SUBD
EQU
Operand
CAT
$12
Comments
FWD REF TO CAT
DEFINE CAT=$12
CAT
93 12
7F 00 12
In the previous example, the first reference to the CAT label is a forward reference,
and the assembler selected the extended addressing mode. The second reference,
SUBD
CLR
CAT
CAT
BKWD REF TO CAT
EXTENDED ONLY