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參數(shù)資料
| 型號(hào)： | MC68HC11A8BMP2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁(yè)數(shù)： | 119/158頁(yè) |
| 文件大?。?/td> | 3803K |
| 代理商： | MC68HC11A8BMP2 |
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SERIAL PERIPHERAL INTERFACE
MOTOROLA
TECHNICAL DATA
6-5
6
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, a steady state
low value is produced at the SCK pin of the master device. Conversely, if this bit is set,
the SCK pin will idle high. This bit is also used in conjunction with the clock phase con-
trol bit to produce the desired clock-data relationship between master and slave. See
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-
ship between master and slave. The CPOL bit can be thought of as simply inserting
an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally
different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
As soon as SS goes low the transaction begins and the first edge on SCK invokes the
first data sample. When CPHA = 1, the SS pin may be thought of as a simple output
enable control. Refer to Figure 6-1.
SPR1 and SPR0—SPI Clock Rate Selects
These two serial peripheral rate bits select one of four baud rates (Table 6-1) to be
used as SCK if the device is a master; however, they have no effect in the slave mode.
6.4.2 Serial Peripheral Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of data transfer be-
tween the processor and external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. Clearing the SPIF bit is accomplished by reading the
SPSR (with SPIF set) followed by an access of the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write to SPDR are inhibited.
Table 6-1 Serial Peripheral Rate Selection
SPR1
SPR0
Internal Processor,
Clock Divide By
00
2
01
4
10
16
11
32
7
654321
0
$1029
SPIF
WCOL
0
MODF
0000
SPSR
RESET
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC11A8BVP2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
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| MC68HC11A8P1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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