參數(shù)資料
型號： MC68HC11A8BMP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 122/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A8BMP2
ANALOG-TO-DIGITAL CONVERTER
MC68HC11A8
7-2
TECHNICAL DATA
7
7.3 Single-Channel Operation
There are two variations of single-channel operation. In the first variation (SCAN = 0),
the single selected channel is converted four consecutive times with the first result be-
ing stored in A/D result register 1 (ADR1) and the fourth result being stored in register
ADR4. After the fourth conversion is complete, all conversion activity is halted until a
new conversion command is written to the ADCTL register. In the second variation
(SCAN = 1), conversions continue to be performed on the selected channel with the
fifth conversion being stored in register ADR1 (overwriting the first conversion result),
the sixth conversion overwrites ADR2, and so on.
Figure 7-1 A/D Conversion Sequence
Figure 7-2 A/D Pin Model
7.4 Multiple-Channel Operation
There are two variations in multiple-channel operation. In the first variation (SCAN =
0), the selected group of four channels are converted, one time each, with the first re-
sult being stored in register ADR1 and the fourth result being stored in register ADR4.
After the fourth conversion is complete, all conversion activity is halted until a new con-
version command is written to the ADCTL register. In the second variation (SCAN =
1), conversions continue to be performed on the selected group of channels with the
fifth conversion being stored in register ADR1 (replacing the earlier conversion result
for the first channel in the group), the sixth conversion overwrites ADR2, and so on.
0
32
64
96
128 — E CYCLES
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
MSB
4
CYCLES
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
REPEAT
SEQUENCE,
SCAN
=
1
SET
CC
FLAG
CONVERT FIRST
CHANNEL, UPDATE
ADR1
CONVERT SECOND
CHANNEL, UPDATE
ADR2
CONVERT THIRD
CHANNEL, UPDATE
ADR3
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
12 E CYCLES
WRITE
TO
ADCTL
E CLOCK
DIFFUSION/POLY
< 2 pF
COUPLER
400 nA
JUNCTION
LEAKAGE
+ ~20V
– ~0.7V
*
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
VRL
INPUT
+ ~12V
– ~0.7V
PROTECTION
DEVICE
≤ 4 K
DUMMY N-CHANNEL
OUTPUT DEVICE
ANALOG
INPUT
PIN
~ 20 pF
DAC
CAPACITANCE
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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