參數(shù)資料
型號： MC68HC11A8BMP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 50/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A8BMP2
ELECTRICAL CHARACTERISTICS
MOTOROLA
TECHNICAL DATA
A-23
A
NOTES:
1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
Table A-8a Serial Peripheral Interface (SPI) Timing (MC68L11A8)
VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH
Num
Characteristic
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Operating Frequency
Master
Slave
fop(m)
fop(s)
dc
0.5
1.0
dc
0.5
2.0
fop
MHz
1
Cycle Time
Master
Slave
tcyc(m)
tcyc(s)
2.0
1000
—
2.0
500
—
tcyc
ns
2
Enable Lead Time
Master
(Note 2)
Slave
tlead(m)
tlead(s)
—
500
—
250
—
ns
3
Enable Lag Time
Master
(Note 2)
Slave
tlag(m)
tlag(s)
—
500
—
250
—
ns
4
Clock (SCK) High Time
Master
Slave
tw(SCKH)m
tw(SCKH)s
680
380
—
340
190
—
ns
5
Clock (SCK) Low Time
Master
Slave
tw(SCKL)m
tw(SCKL)s
680
380
—
340
190
—
ns
6
Data Setup Time (Inputs)
Master
Slave
tsu(m)
tsu(s)
100
—
100
—
ns
7
Data Hold Time (Inputs)
Master
Slave
th(m)
th(s)
100
—
100
—
ns
8
Access Time (Time to Data Active from High-
Impedance State)
Slave
ta
0
120
0
120
ns
9
Disable Time (Hold Time to High-Impedance State)
Slave
tdis
—
240
—
240
ns
10
Data Valid (After Enable Edge)(Note 3)
tv(s)
—
240
—
240
ns
11
Data Hold Time (Outputs) (After Enable Edge)
tho
0—0—
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
trm
trs
—
100
2.0
—
100
2.0
ns
s
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tfm
tfs
—
100
2.0
—
100
2.0
ns
s
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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