- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45232 > MC68HC11P1CFN3R2 (MOTOROLA INC) 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC84 PDF資料下載
參數(shù)資料
| 型號： | MC68HC11P1CFN3R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 229/236頁 |
| 文件大?。?/td> | 1232K |
| 代理商： | MC68HC11P1CFN3R2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁當(dāng)前第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁
MOTOROLA
5-12
MC68HC11P2
SERIAL COMMUNICATIONS INTERFACE
5
5.7
Status ags and interrupts
The SCI transmitter has two status ags. These status ags can be read by software (polled) to
tell when certain conditions exist. Alternatively, a local interrupt enable bit can be set to enable
each of these status conditions to generate interrupt requests. Status ags are automatically set
by hardware logic conditions, but must be cleared by software. This provides an interlock
mechanism that enables logic to know when software has noticed the status indication. The
software clearing sequence for these ags is automatic — functions that are normally performed
in response to the status ags also satisfy the conditions of the clearing sequence.
TDRE and TC ags are normally set when the transmitter is rst enabled (TE set to one). The
TDRE ag indicates there is room in the transmit queue to store another data character in the
transmit data register. The TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE
must be polled. When TIE and TDRE are one, an interrupt is requested.
The TC ag indicates the transmitter has completed the queue. The TCIE bit is the local interrupt
mask for TC. When TCIE is zero, TC must be polled; when TCIE is one and TC is one, an interrupt
is requested.
Writing a zero to TE requests that the transmitter stop when it can. The transmitter completes any
transmission in progress before shutting down. Only an MCU reset can cause the transmitter to
stop and shut down immediately. If TE is cleared when the transmitter is already idle, the pin
reverts to its general-purpose I/O function (synchronized to the bit-rate clock). If anything is being
transmitted when TE is cleared, that character is completed before the pin reverts to
general-purpose I/O, but any other characters waiting in the transmit queue are lost. The TC and
TDRE ags are set at the completion of this last character, even though TE has been disabled.
5.7.1
Receiver ags
The SCI receiver has seven status ags, three of which can generate interrupt requests. The status
ags are set by the SCI logic in response to specic conditions in the receiver.These ags can be read
(polled) at any time by software. Refer to Figure 5-3, which shows SCI interrupt arbitration.
When an overrun takes place, the new character is lost, and the character that was in its way in
the parallel receive data register (RDR) is undisturbed. RDRF is set when a character has been
received and transferred into the parallel RDR. The OR ag is set instead of RDRF if overrun
occurs. A new character is ready to be transferred into the RDR before a previous character is read
from the RDR.
The NF, FE and PF ags provide additional information about the character in the RDR, but do not
generate interrupt requests.
The receiver active ag (RAF) indicates that the receiver is busy.
The last receiver status ag and interrupt source come from the IDLE ag. The RXD line is idle if it has
constantly been at logic one for a full character time. The IDLE ag is set only after the RXD line has
been busy and becomes idle. This prevents repeated interrupts for the time RXD remains idle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC711P2CFN3R2 | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC711P2CFN4R2 | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11P3CFN4R2 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11P1CFN4R2 | 8-BIT, EEPROM, 4 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11P2BCFN4R2 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC16Z1CAG | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC16Z1CAG16 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MC68HC16Z1CAG16 | 制造商:Freescale Semiconductor 功能描述:IC16-BIT MICROCONTROLLER |
| MC68HC16Z1CAG20 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| MC68HC16Z1CAG20 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。