
MC68HC11P2
MOTOROLA
v
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
7
SERIAL PERIPHERAL INTERFACE
7.1
Functional description............................................................................................7-1
7.2
SPI transfer formats ...............................................................................................7-2
7.2.1
Clock phase and polarity controls ....................................................................7-3
7.3
SPI signals.............................................................................................................7-3
7.3.1
Master in slave out ...........................................................................................7-4
7.3.2
Master out slave in ...........................................................................................7-4
7.3.3
Serial clock.......................................................................................................7-4
7.3.4
Slave select......................................................................................................7-4
7.4
SPI system errors ..................................................................................................7-5
7.5
SPI registers ..........................................................................................................7-5
7.5.1
SPCR — Serial peripheral control register ......................................................7-6
7.5.2
SPSR — Serial peripheral status register........................................................7-7
7.5.3
SPDR — SPI data register...............................................................................7-8
7.5.4
OPT2 — System conguration options register 2 ............................................7-9
8
TIMING SYSTEM
8.1
Timer structure ......................................................................................................8-2
8.2
Input capture..........................................................................................................8-5
8.2.1
TCTL2 — Timer control register 2....................................................................8-5
8.2.2
TIC1–TIC3 — Timer input capture registers ....................................................8-6
8.2.3
TI4/O5 — Timer input capture 4/output compare 5 register.............................8-7
8.3
Output compare .....................................................................................................8-7
8.3.1
TOC1–TOC4 — Timer output compare registers.............................................8-8
8.3.2
CFORC — Timer compare force register.........................................................8-8
8.3.3
OC1M — Output compare 1 mask register......................................................8-9
8.3.4
OC1D — Output compare 1 data register........................................................8-9
8.3.5
TCNT — Timer counter register.......................................................................8-10
8.3.6
TCTL1 — Timer control register 1....................................................................8-10
8.3.7
TMSK1 — Timer interrupt mask register 1.......................................................8-11
8.3.8
TFLG1 — Timer interrupt ag register 1 ..........................................................8-11
8.3.9
TMSK2 — Timer interrupt mask register 2.......................................................8-12
8.3.10
TFLG2 — Timer interrupt ag register 2 ..........................................................8-13
8.4
Real-time interrupt .................................................................................................8-14
8.4.1
TMSK2 — Timer interrupt mask register 2.......................................................8-14
8.4.2
TFLG2 — Timer interrupt ag register 2 ..........................................................8-15
8.4.3
PACTL — Pulse accumulator control register ..................................................8-16
8.5
Computer operating properly watchdog function ...................................................8-16
8.6
Pulse accumulator .................................................................................................8-16
8.6.1
PACTL — Pulse accumulator control register ..................................................8-18
8.6.2
PACNT — Pulse accumulator count register ...................................................8-19