Advance Information
MC68HC912B32 MC68HC12BE32 — Rev. 3.0
22
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
13-43 Data Direction Register for Timer Port (DDRT) . . . . . . . . . . .263
13-44 16-Bit Pulse Accumulator B Control Register (PBCTL) . . . . .264
13-45 Pulse Accumulator B Flag Register (PBFLG). . . . . . . . . . . . .265
13-46 8-Bit Pulse Accumulator Holding Register 3 (PA3H) . . . . . . .265
13-47 8-Bit Pulse Accumulator Holding Register 2 (PA2H) . . . . . . .265
13-48 8-Bit Pulse Accumulator Holding Register 1 (PA1H) . . . . . . .266
13-49 8-Bit Pulse Accumulator Holding Register 0 (PA0H) . . . . . . .266
13-50 Modulus Down-Counter Count Registers (MCCNT). . . . . . . .267
13-51 Timer Input Capture Holding Register 0 (TC0H) . . . . . . . . . .268
13-52 Timer Input Capture Holding Register 1 (TC1H) . . . . . . . . . .268
13-53 Timer Input Capture Holding Register 2 (TC2H) . . . . . . . . . .269
13-54 Timer Input Capture Holding Register 3 (TC3H) . . . . . . . . . .269
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10 SCI Data Register Low (SC0DRL) . . . . . . . . . . . . . . . . . . . . .284
14-11 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .286
14-12 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . . .287
14-13 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . . .288
14-14 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .289
14-15 SPI Control Register 1 (SP0CR1). . . . . . . . . . . . . . . . . . . . . .290
14-16 SPI Control Register 2 (SP0CR2). . . . . . . . . . . . . . . . . . . . . .292
14-17 SPI Baud Rate Register (SP0BR) . . . . . . . . . . . . . . . . . . . . .293
14-18 SPI Status Register (SP0SR). . . . . . . . . . . . . . . . . . . . . . . . .294
14-19 SPI Data Register (SP0DR) . . . . . . . . . . . . . . . . . . . . . . . . . .295
14-20 Port S Data Register (PORTS). . . . . . . . . . . . . . . . . . . . . . . .296
14-21 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . .297
14-22 Pullup and Reduced Drive Register for Port S (PURDS) . . . .298
Serial Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . .272
Serial Communications Interface Block Diagram . . . . . . . . . .274
SCI Baud Rate Control Register (SC0BDH). . . . . . . . . . . . . .276
SCI Baud Rate Control Register (SC0BDL) . . . . . . . . . . . . . .276
SCI Control Register 1 (SC0CR1) . . . . . . . . . . . . . . . . . . . . .277
SCI Control Register 2 (SC0CR2) . . . . . . . . . . . . . . . . . . . . .280
SCI Status Register 1 (SC0SR1) . . . . . . . . . . . . . . . . . . . . . .281
SCI Status Register 2 (SC0SR2) . . . . . . . . . . . . . . . . . . . . . .283
SCI Data Register High (SC0DRH) . . . . . . . . . . . . . . . . . . . .284