List of Figures
MC68HC912B32 MC68HC12BE32 — Rev. 3.0
Advance Information
MOTOROLA
List of Figures
23
Figure
Title
Page
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10 J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . . . .327
15-11 BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . . .328
15-12 BDLC Control Register 1 (BCR1). . . . . . . . . . . . . . . . . . . . . .333
15-13 BDLC Control Register 2 (BCR2). . . . . . . . . . . . . . . . . . . . . .335
15-14 Types of In-Frame Response. . . . . . . . . . . . . . . . . . . . . . . . .338
15-15 BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . . .342
15-16 BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . . .345
15-17 BDLC Analog Roundtrip Delay Register (BARD) . . . . . . . . . .346
15-18 Port DLC Control Register (DLCSCR) . . . . . . . . . . . . . . . . . .348
15-19 Port DLC Data Register (PORTDLC) . . . . . . . . . . . . . . . . . . .349
15-20 Port DLC Data Direction Register (DDRDLC) . . . . . . . . . . . .350
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . .307
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . .313
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . . . .315
J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . .319
J1850 VPW Received Passive Symbol Times . . . . . . . . . . . .322
VPW Received Passive EOF and IFS Symbol Times . . . . . .323
J1850 VPW Received Active Symbol Times . . . . . . . . . . . . .325
J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . .325
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10 Port AD Data Input Register (PORTAD). . . . . . . . . . . . . . . . .363
16-11 ATD Result Registers High. . . . . . . . . . . . . . . . . . . . . . . . . . .364
16-12 ATD Result Registers Low . . . . . . . . . . . . . . . . . . . . . . . . . . .364
ATD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
ATD Control Register 0 (ATDCTL0). . . . . . . . . . . . . . . . . . . .354
Reserved (ATDCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
ATD Control Register 2 (ATDCTL2). . . . . . . . . . . . . . . . . . . .355
ATD Control Register 3 (ATDCTL3). . . . . . . . . . . . . . . . . . . .356
ATD Control Register 4 (ATDCTL4). . . . . . . . . . . . . . . . . . . .357
ATD Control Register 5 (ATDCTL5). . . . . . . . . . . . . . . . . . . .359
ATD Status Register (ATDSTAT). . . . . . . . . . . . . . . . . . . . . .361
ATD Test Register (ATDSTAT) . . . . . . . . . . . . . . . . . . . . . . .362
17-1
17-2
BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .373
BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .374