參數(shù)資料
型號(hào): MC68HC16S2CPU20
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 21/104頁(yè)
文件大?。?/td> 640K
代理商: MC68HC16S2CPU20
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
23
3.4.6 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts at user-programmable intervals. Timing for the
PIT is provided by a programmable prescaler driven by the system clock.
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
Table 12 shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT
interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT interrupt is ser-
viced first. The periodic timer continues to run when the interrupt is disabled.
PIV[7:0] — Periodic Interrupt Vector
This bit field contains the vector generated in response to an interrupt from the periodic timer. When the
SIM responds, the periodic interrupt vector is placed on the bus.
PITR contains the count value for the periodic timer. Setting the PITM[7:0] field turns off the periodic
timer. This register can be read or written at any time.
PTP — Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by 512
The reset state of PTP is the complement of the state of the MODCLK signal at the rising edge of
RESET.
PICR — Periodic Interrupt Control Register
$YFFA22
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIRQL[2:0]
PIV[7:0]
RESET:
0
1
Table 12 Periodic Interrupt Request Levels
PIRQL[2:0]
Interrupt Request Level
000
Periodic interrupt disabled
001
Interrupt request level 1
010
Interrupt request level 2
011
Interrupt request level 3
100
Interrupt request level 4
101
Interrupt request level 5
110
Interrupt request level 6
111
Interrupt request level 7
PITR — Periodic Interrupt Timer Register
$YFFA24
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PTP
PITM[7:0]
RESET:
0
MODCLK
0
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