參數(shù)資料
型號(hào): MC68HC16S2CPU20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 75/104頁
文件大小: 640K
代理商: MC68HC16S2CPU20
MOTOROLA
MC68HC16S2
72
MC68HC16S2TS/D
STOP — Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is one, leaving
the array configured for LPSTOP operation. In stop mode, the array retains its contents, but cannot be
read or written by the CPU. This bit can be read or written at any time.
RLCK — RAM Base Address Lock
0 = SRAM base address registers can be written from IMB
1 = SRAM base address registers are locked
RLCK defaults to zero on reset. It can be written to one once.
RASP[1:0] — RAM Array Space
This field limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 operates in supervisor mode only, RASP1 has no effect. Refer
RAMTST — RAM Test Register
$YFFB02
RAMTST is for factory test only. Reads of this register return zeros and writes have no effect.
RAMBAH and RAMBAL specify an SRAM base address in the system memory map. They can only be
written while the SRAM is in low-power mode (RAMMCR STOP = 1, the default out of reset) and the
base address lock is disabled (RAMMCR RLCK = 0, the default out of reset). This prevents accidental
remapping of the array. Because the CPU16 drives ADDR[23:20] to the same logic level as ADDR19,
the values of the RAMBAH ADDR[23:20] fields must match the value of the ADDR19 field for the array
to be accessible.
Table 37 RASP Encoding
RASP
Space
X0
Program and data
X1
Program
RAMBAH — Array Base Address Register High
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
RESET:
0
RAMBAL — Array Base Address Register Low
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT USED
RESET:
0
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