參數(shù)資料
型號: MC68HC16S2CPU20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 34/104頁
文件大小: 640K
代理商: MC68HC16S2CPU20
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
35
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip-select in asynchronous mode. Selecting address
strobe causes chip-select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip-select to be asserted synchronized with data strobe.
DSACK[3:0] — Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. Table 26 shows the DSACK[3:0] encoding. The fast termi-
nation encoding (%1110) is used for two-cycle access to external memory.
SPACE[1:0] — Address Space
Use this option field to select an address space for the chip-select logic. The CPU16 normally operates
in supervisor space, but interrupt acknowledge cycles must take place in CPU space. Table 27 shows
address space bit encodings.
Table 25 R/W Encodings
R/W[1:0]
Description
00
Reserved
01
Read only
10
Write only
11
Read/Write
Table 26 DSACK Field Encoding
DSACK[3:0]
Clock Cycles Required
Per Access
Wait States
Per Access
0000
3
0 Wait states
0001
4
1 Wait state
0010
5
2 Wait states
0011
6
3 Wait states
0100
7
4 Wait states
0101
8
5 Wait states
0110
9
6 Wait states
0111
10
7 Wait states
1000
11
8 Wait states
1001
12
9 Wait states
1010
13
10 Wait states
1011
14
11 Wait states
1100
15
12 Wait states
1101
16
13 Wait states
1110
2
Fast termination
1111
External DSACK
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