參數(shù)資料
型號: MC68HC16S2CPU20
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 85/104頁
文件大?。?/td> 640K
代理商: MC68HC16S2CPU20
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
81
NOTES:
1. Applies to:
SIZ[1:0], AS, DS, IRQ[7:1], MODCLK, RESET, EXTAL, TSC, BKPT/DSCLK, IPIPE1/DSI
2. Input-Only Pins: EXTAL, TSC, BKPT/DSCLK
Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, IPIPE0/DSO
Input/Output Pins:
Group 1: DATA[15:0], IPIPE1/DSI
Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E[7:0] — SIZ[1:0], AS, DS, AVEC, DSACK[1:0]
Port F[7:0] —IRQ[7:1], MODCLK, ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0,
BGACK/CS2
Group 3: HALT, RESET
3. Does not apply to HALT and RESET because they are open drain pins.
4. Use of an active pulldown device is recommended.
5. Total operating current is the sum of the appropriate VDD, supply and VDDSYN supply current. VDD at 3.3V.
6. Current measured with system clock frequency of 20.97 MHz, all modules active.
7. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5
volts. The SRAM array cannot be accessed while the module is in standby mode.
8. When VSB is more than 0.3V greater than VDD, current flows between the VSTBY and VDD pins, which causes
standby current to increase toward the maximum transient condition specification. System noise on the VDD
and VSTBY pin can contribute to this condition.
9. Power dissipation is measured with a system clock frequency of 20.97 MHz, all modules active. Power dissi-
pation is calculated using the following expression:
PD = Maximum VDD (IDD + IDDSYN + ISB)
10. Input capacitance is periodically sampled rather than 100% tested.
19
Load Capacitance2
Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE0
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O Pins
Group 4 I/O Pins
CL
90
100
130
200
pF
Table 44 20.97 MHz DC Characteristics (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
Num
Characteristic
Symbol
Min
Max
Unit
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