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| 型號： | MC68HC16Y1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁數(shù)： | 102/122頁 |
| 文件大小： | 749K |
| 代理商： | MC68HC16Y1 |
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MOTOROLA
102
MC68HC16Y1
MC68HC16Y1TS/D
7.1.1 MCCI Global Registers
Global registers contain parameters used by both the SPI and the SCI submodules. These parameters
are used by the MCCI to interface with the CPU and other system modules.
STOP — Stop Enable
0 = Normal MCCI clock operation
1 = MCCI clock operation stopped
STOP places the MCCI into a low power state by disabling the system clock in most parts of the module.
MMCR is the only register guaranteed to be readable while STOP is asserted. STOP may be negated
by the CPU and by reset.
Bits [14:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
In systems with controlled access levels, SUPV places assignable registers in either supervisor-only
data space or unrestricted data space. All MCCI registers reside in supervisor-only space. Because the
CPU16 in the MC68HC16Y1 operates only in supervisor mode, SUPV has no meaning.
Bits [6:4] — Not Implemented
IARB — Interrupt Arbitration Identification Number
Each module that generates interrupts has an IARB field. The value in this field is used to arbitrate be-
tween simultaneous interrupt requests of the same priority. The reset value of all IARB fields other than
that of the SCIM is $0 (lowest priority), to prevent priority conflict during initialization. The IARB field
must be initialized to a value between $F (highest priority) and $1 (lowest priority), or subsequent inter-
rupt requests will be identified by the CPU as spurious.
MTEST
— MCCI Test Register
MTEST is used in conjunction with SCIM test functions during factory test of the MCCI. Accesses to
MTEST must be made while the MCU is in test mode.
$YFFC02
ILSCI determines the priority level of interrupts requested by each SCI. Separate fields hold interrupt
priority values for SCIA and SCIB. Priority is used to determine which interrupt is serviced first when two
or more modules or external peripherals simultaneously request an interrupt.
ILSCIA, ILSCIB — Interrupt Level for SCIA, SCIB
ILSCIA, ILSCIB determine the priority levels of SCIA and SCIB interrupts, respectively. This field must
contain a value between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized.
MMCR
— MCCI Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
0
0
0
0
0
0
0
SUPV
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
ILSCI/MIVR
— SCI Interrupt Request Level Register/MCCI Interrupt Vector Register
$YFFC04
15
14
13
12
11
10
9
8
7
1
0
0
0
ILSCIB
ILSCIA
MIVR
1
1
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
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