參數(shù)資料
型號: MC68HC16Y1
廠商: Motorola, Inc.
英文描述: 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述: 16位微控制器模塊(16位模塊化微控制器)
文件頁數(shù): 73/122頁
文件大小: 749K
代理商: MC68HC16Y1
MC68HC16Y1
MC68HC16Y1TS/D
MOTOROLA
73
HOT4 — Hang on T4
0 = Exit wait on T4 state caused by assertion of HOT4
1 = Enter wait on T4 state
DSCR[14:11] — Not Implemented
BLC — Branch Latch Control
1 = Do not latch conditions into branch condition register before exiting the halted state or during
the time-slot transition period.
0 = Latch conditions into branch condition register prior to exiting halted state.
CLKS — Stop Clocks (to TCRs)
0 = Do not stop TCRs.
1 = Stop TCRs during the halted state.
FRZ[1:0] — IMB FREEZE Response
The FRZ bits specify the TPU microengine response to the FREEZE signal.
CCL — Channel Conditions Latch
CCL controls the latching of channel conditions (MRL and TDL) when CHAN is written.
0 = Only the pin state condition of the new channel is latched as a result of the write CHAN register
microinstruction.
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write CHAN
register microinstruction.
BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits
DSCR[5:0] are TPU breakpoint enables. Setting a bit enables a breakpoint condition.
BP —Break if
μ
PC equals
μ
PC breakpoint register.
BC —Break if CHAN register equals channel breakpoint register at beginning of state or when
CHAN is changed through microcode.
BH —Break if host service latch is asserted at beginning of state.
BL —Break if link service latch is asserted at beginning of state.
BM —Break if MRL is asserted at beginning of state.
BT —Break if TDL is asserted at beginning of state.
DSSR[15:8, 2:0] — Not Implemented
DSCR
— Development Support Control Register
$YFFE04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HOT4
0
0
0
0
BLC
CLKS
FRZ
CCL
BP
BC
BH
BL
BM
BT
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRZ[1:0]
00
01
10
11
TPU Response
Ignore Freeze
Reserved
Freeze at End of Current Microcycle
Freeze at Next Time-Slot Boundary
DSSR
— Development Support Status Register
$YFFE06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BKPT
PCBK
CHBK
SRBK
TPUF
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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