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| 型號： | MC68HC2681P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 13/88頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MC68HC2681P |
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Signal Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
2-3
2
2.3 CRYSTAL INPUT (X2)
This input is an additional connection to a crystal (see Section 2 Signal Descriptions). If an
external CMOS-level clock is used, this pin must be left open. If a crystal is used, a capacitor
of approximately 10 to 15 picofarads should be connected from this pin to ground.
2.4 RESET (RESET)
The DUART can be reset by asserting the RESET signal or by programming the appropriate
command register. A hardware reset (assertion of RESET) clears the following registers:
Status registers A and B (SRA and SRB)
Interrupt mask register (IMR)
Interrupt status register (ISR)
Output port register (OPR)
Output port configuration register (OPCR)
RESET performs the following operations:
Initializes the interrupt vector register (IVR) to 0F16
Places parallel outputs OP0 through OP7 in the high state
Places the counter/timer in timer mode
Places channels A and B in the inactive state with the transmitter serial-data outputs
(TxDA and TxDB) in the mark (high) state.
Software resets are not as encompassing and are achieved by appropriately programming
the channel A and/or B command registers. Reset commands can be programmed through
the command register to reset the receiver, transmitter, error status, or break-change
interrupts for each channel. Refer to Section 4 Programming and Register Descriptions
for more information.
2.5 CHIP-SELECT (CS)
This active-low input signal, when low, enables data transfers between the CPU and DUART
on the data lines (D0 through D7). These data transfers are controlled by read/write (R/W)
and the register-select inputs (RS1 through RS4). When chip-select is high, the D0 through
D7 data lines are placed in the high-impedance state.
2.6 READ/WRITE (R/W)
When high, this input indicates a read cycle; when low, it indicates a write cycle. Assertion
of the chip-select input initiates a cycle.
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