參數(shù)資料
型號(hào)： MC68HC2681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 14/88頁(yè)
文件大?。?/td> 461K
代理商： MC68HC2681P
Signal Descriptions
2-4
MC68HC681 USER’S MANUAL
MOTOROLA
2
2.7 DATA TRANSFER ACKOWLEDGE (DTACK)
This three-state active low output is asserted in read, write, or interrupt-acknowledge (IACK)
cycles to indicate the proper transfer of data between the CPU and DUART. If there is no
pending interrupt on an IACK cycle, DTACK is not asserted. DTACK is an “active rescind”
signal: at the end of a transfer, it drives high momentarily, then is three-stated so that it can
be wire-ANDed with other DTACK sources, like an open-drain signal.
2.8 REGISTER-SELECT BUS (RS1–RS4)
The register-select bus lines during read/write operations select the DUART internal
registers, ports, or commands.
2.9 DATA BUS (D0–D7)
These bidirectional three-state data lines transfer commands, data, and status between the
CPU and DUART. D0 is the least-significant bit.
2.10 INTERUPT REQUEST (IRQ)
This active-low, open-drain output signals the CPU that one or more of the eight maskable
interrupting conditions are true.
2.11 INTERUPT ACKOWLEDGE (IACK)
This active-low input indicates an interrupt-acknowledge cycle. If there is an interrupt
pending (IRQ asserted) and this pin is asserted, the DUART responds by placing the
interrupt vector on the data bus and then asserting DTACK. If there is no interrupt pending
(IRQ negated), the DUART ignores this pin.
2.12 CHANNEL A/B TRANSMITTER SERIAL-DATA OUTPUT (TxDA/TxDB)
The independent transmitter serial-data outputs for channel A and B transmit the
least-significant bit first. The output is held high (mark condition) when its associated
transmitter is disabled, idle, or operating in the local loopback mode. (‘‘Mark’’ is high and
‘‘space’’ is low.) Data is shifted out from this pin on the falling edge of the programmed clock
source.
2.13 CHANNEL A/B RECEIVER SERIAL-DATA INPUT (RxDA/RxDB)
The independent receiver serial-data inputs for channel A and B receive the least-significant
bit first. Data on these pins is sampled on the rising edge of the programmed clock source.
2.14 PARALLEL INPUTS (IP0–IP5)
The parallel inputs can be used as general-purpose inputs. However, each pin also has an
alternate function(s) described below.
2.14.1 IP0
This input can be used as the channel A clear-to-send active-low input (CTSA). A change-of-
state detector is also associated with this input.
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