參數(shù)資料
型號(hào): MC68HC2681P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 5/88頁
文件大?。?/td> 461K
代理商: MC68HC2681P
Introduction
1-2
MC68HC681 USER’S MANUAL
MOTOROLA
1
Figure 1-1. MC68HC681 Block Diagram
INTERNAL CONTROL LOGIC
CHANNEL A
RS4-RS1
EXTERNAL
INTERFACE
TxDA
RxDA
X1
X2
PROCESSOR
INTERFACE
VCC
IRQ
DTACK
R/W
CS
INTERNAL
D
AT
A
B
U
S
CRA
COMMAND REGISTER
W
MR1A
MODE REGISTER
1
R/W
MR2A
MODE REGISTER 2
R/W
SRA
STATUS REGISTER
R
THRA
TRANSMIT HOLDING REG
W
RHRA
RECEIVE HOLDING REG (3)
R
RHRA (2)
TBA
RBA
TRANSMIT SHIFT REG
RHRA (1)
RECEIVE SHIFT REGISTER
CHANNEL B
TxDB
RxDB
CRB
COMMAND REGISTER
W
MR1B
MODE REGISTER 1
R/W
MR2B
MODE REGISTER 2
R/W
SRB
STATUS REGISTER
R
THRB
TRANSMIT HOLDING REG
W
RHRB
RECEIVE HOLDING REG (3)
R
RHRB (2)
TBB
RBB
TRANSMIT SHIFT REGISTER
RHRB (1)
RECEIVE SHIFT REGISTER
INPUT PORT
IPCR
INPUT PORT CHANGE REG
R
AUX CONTROL REG (4 BITS)
W
ACR
INPUT PORT (6 BITS)
R
ACR
*
Same ACR as in Interrupt Control Logic
*
OUTPUT PORT
OPCR
OUTPUT PORT CONFIG REG
W
OUTPUT PORT REG (8 BITS)
W
OPR
FIFO
TIMING LOGIC
Current Count in Counter Mode may be Read
*
INTERRUPT CONTROL LOGIC
IMR
INTERRUPT MASK REG
W
INTERRUPT STATUS REG
R
AUX CONTROL REG (4 BITS)
W
ACR
*
Same ACR as in Input Port
*
D7-D0
DATA BUS BUFFER
CSRA CHANNEL A CLOCK SELECT REG
W
CHANNEL B CLOCK SELECT REG
W
ACR
AUXILIARY CONTROL REG (4 BITS) W
CSRB
COUNTER/TIMER
UPPER REGISTER
(MOST SIGNIF 8 BITS)
W
*
COUNTER/TIMER
LOWER REGISTER
(LEAST SIGNIF 8 BITS)
W
*
ISR
GND
OP7-OP0
RESET
IP5-IP0
INTERRUPT VECTOR REG
R/W
IVR
IACK
FIFO
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