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參數(shù)資料
| 型號： | MC68HC2681P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 18/88頁 |
| 文件大小： | 461K |
| 代理商： | MC68HC2681P |
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Operation
3-2
MC68HC681 USER’S MANUAL
MOTOROLA
3
A send-break is deferred as long as the transmitter has characters to send, but if normal
character transmission is inhibited by CTS, the send-break will proceed. The send-break
must be terminated by a stop-break, disable, or reset before normal character transmission
can resume.
Customers can program the transmitter to automatically negate the request-to-send (RTS)
output (alternate function of OP0 and OP1) on completion of a message transmission. If the
transmitter is programmed to operate in this manner, the RTS output must be manually
asserted before each message is transmitted. If OP0 (or OP1) is programmed in automatic
RTS mode, the RTS output will be automatically negated when the transmitter is disabled
and the transmit-shift register and holding register are both empty. In automatic RTS mode,
a character in the holding register is not held back by a disable, but no more characters can
be written to the holding register after the transmitter is disabled.
3.2 RECEIVER
The channel A and B receivers are enabled for data reception through the respective
channel’s command register. The channel’s receiver looks for the high-to-low (mark-to-
space) transition of a start bit on the receiver serial-data input pin. If operating in 16X clock
mode, the serial input data is re-sampled on the next 7 clocks. If the receiver serial data is
sampled high, the start bit is invalid and the search for a valid start bit begins again. If
receiver serial data is still low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals (at the theoretical center of the bit) until the proper
number of data bits and the parity bit (if any) have been assembled and one stop bit has
been detected. Data on the receiver serial data input pin is sampled on the rising edge of
the programmed clock source.
During this process, the least-significant bit is received first. The data is then transferred to
a receive holding register (RHR) and the receiver-ready bit in the status register (SRA or
SRB) is set to a one (see Figure 3-1). This condition can be programmed to generate an
interrupt request on the IRQ output, an interrupt request for channel A’s receiver on parallel
output OP4, or an interrupt request for channel B’s receiver on parallel output OP5. If the
character length is less than eight bits, the most significant unused bits in the receive holding
register (RHR) are set to zero.
If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit.
However, if the stop bit is sampled as a 0, either a framing error or a received break has
occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing
error; the damaged character is transferred to a holding register with the framing error flag
set. If the receiver serial data remains low for one-half of the bit period after the stop bit was
sampled, the receiver operates as if a new start bit transition has been detected. If the stop
bit is 0 and the data and parity (if any) are also all zero, it is a break. A character consisting
of all zeros will be loaded into a receive holding register (RHR) with the received-break bit
(but not the framing error bit) set to a one. The receiver serial-data input must return to a
high condition for at least one-half bit time before a search for the next start bit begins.
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