參數(shù)資料
型號： MC68HC2681P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 17/88頁
文件大?。?/td> 461K
代理商： MC68HC2681P
MOTOROLA
MC68HC681 USER’S MANUAL
3-1
3
SECTION 3
OPERATION
3.1 TRANSMITTER
The channel A and B transmitters are enabled for data transmission through their respective
command registers (refer to Section 4 Programming and Register Descriptions). The
DUART signals the CPU it is ready to accept a character by setting the transmitter-ready bit
in the channel’s status register. Customers can program this condition to generate an
interrupt request on the IRQ output, an interrupt request for channel A’s transmitter on
parallel output OP6, or for channel B’s transmitter on parallel output OP7. When a character
is loaded into the transmit buffer (TB), the above conditions for the respective channel are
negated. Data is transferred from the transmit holding register to the transmit shift register
when the shift register is idle or has completed transmission of the previous character. The
transmitter ready conditions are then re-asserted, providing one full character time of
buffering. Characters cannot be loaded into the transmit buffer while the transmitter is
disabled.
The transmitter converts the parallel data from the CPU to a serial bit stream on the
transmitter serial-data output pin. It automatically sends a start bit followed by the
programmed number of data bits, an optional parity bit, and the programmed number of stop
bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output
pin on the failing edge of the programmed clock source. After the transmission of the stop
bits, if a new character is not available in the transmit holding register the transmitter
serial-data output remains high and the transmitter-empty bit in the status register (SRA and
SRB) will be set to a one. Transmission resumes and the transmitter-empty bit is cleared
when the CPU loads a new character into the transmit buffer (TBA or TBB). If the transmitter
receives a disable command, it will continue operating until the character in the transmit shift
register is completely sent out. Another character in the holding register is not sent but is not
discarded; it will be sent when the transmitter is re-enabled. The transmitter can be reset
through a software command (refer to Section 2.4 RESET). If it is reset, operation ceases
immediately and must be enabled through the command register before resuming
operation. Reset also discards any character in the holding register.
If clear-to-send (CTS) operation is enabled, the CTS input (alternate function of IP0 or IP1)
must be low in order for the character to be transmitted. If it goes high in the middle of a
transmission, the character in the shift register is transmitted and TxD then remains in the
marking state until CTS again goes low. The transmitter can also be forced to send a
continuous low condition by issuing a send-break command. The state of CTS is ignored by
the transmitter when it is to send a break.
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