參數(shù)資料
型號(hào)： MC68HC805K3DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 55/119頁
文件大小： 496K
代理商： MC68HC805K3DW
General Release Specication
CPU Interrupt Processing
MC68HC805K3 — Rev. 1.0
40
Interrupts
MOTOROLA
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor proceeds with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register states, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending following the stacking operation, the
interrupt with the highest vector location, shown in Table 4-1, is serviced
first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $03F8 through $03FF as defined in Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag Name
Interrupts
CPU
Interrupts
Vector
Addresses
N/A
Reset
RESET
$03FE-$03FF
N/A
Software
SWI
$03FC-$03FD
ISCR
IRQF
External Interrupt
IRQ
$03FA-$03FB
TSCR
TOF
Timer Overow
TIMER
$03F8-$03F9
TSCR
RTIF
Real Time
Interrupt
TIMER
$03F8-$03F9
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