參數(shù)資料
型號： MC68HC805K3DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 57/119頁
文件大?。?/td> 496K
代理商： MC68HC805K3DW
General Release Specication
Reset Interrupt Sequence
MC68HC805K3 — Rev. 1.0
42
Interrupts
MOTOROLA
Figure 4-2. Interrupt Stacking Order
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner. A low-level input on the RESET pin or
an internally generated RST signal causes the program to vector to its
starting address, which is specified by the contents of memory locations
$03FE and $03FF. The I bit in the condition code register also is set. The
MCU is configured to a known state during this type of reset, as
described in Section 5. Resets.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
that were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $03FC and
$03FD.
CONDITION CODE REGISTER
1
PCH
0
ACCUMULATOR
INDEX REGISTER
PCL
R
E
T
U
R
N
DECREASING
MEMORY
ADDRESSES
INCREASING
MEMORY
ADDRESSES
UNSTACK
STACK
I
N
T
E
R
U
P
T
0
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