參數(shù)資料
型號： MC68HC805K3DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 80/119頁
文件大?。?/td> 496K
代理商： MC68HC805K3DW
General Release Specification
Port B
MC68HC805K3 — Rev. 1.0
MOTOROLA
Parallel Input/Output
63
logic zero level, the other PA0–PA3 IRQ inputs are effectively ignored.
Port interrupts will be generated with the above PA0–PA3 I/O state
regardless of whether the port is configured as an input or output.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ pin itself,
and not to the internal IRQ input to the CPU. Therefore, BIH and BIL
cannot be used to test the state of the lower four port A input pins as a
group. Each port A interrupt pin can be tested by reading the port A data
register at $0000.
7.4 Port B
Port B is a 2-bit bidirectional port that shares one of its pins with the RC
oscillator as shown in Figure 7-3. Each port B pin is controlled by the
corresponding bits in a data direction register, a data register, and a
pulldown register.
The port B data register is located at address $0001. The port B data
direction register (DDRB) is located at address $0005, and the port B
pulldown register (PDRB) is located at address $0011. Reset clears both
the DDRB and the PDRB. The port B data register is unaffected by reset.
7.4.1 Port B Data Register
Each port B I/O pin has a corresponding bit in the port B data register.
When a port B pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port B pin is programmed as an input, any read of the port B data
register returns the logic state of the corresponding I/O pin, and any write
to the port B data register is saved in the data register, but not applied to
the corresponding I/O pin. Unused bits 2 through 7 are always read as
logic zeros, and any write to these bits is ignored. The port B data
register is unaffected by reset. The port B data register is indeterminant
after initial power-up.
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