
IRQ Pin
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
Freescale Semiconductor
101
Figure 8-2. IRQ Module Block Diagram
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in
the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$001D
IRQ Status and Control
Register (INTSCR)
See page 102.
Read:
0
0
0
0
IRQF
0
IMASK
MODE
Write:
ACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. IRQ I/O Register Summary
IMASK
D
Q
CK
CLR
IRQ
INTERRUPT
REQUEST
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
V
DD
MODE
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
I
RESET
V
DD
INTERNAL
PULLUP
DEVICE
ACK
IRQ
SYNCHRONIZER