
FLASH Memory
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
Freescale Semiconductor
39
2.6.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 16 Kbyte FLASH array for mass erase operation.
1 = MASS erase operation selected
0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
2.6.3 FLASH Page Erase Operation
Use the following procedure to erase a page (64 bytes) of FLASH memory. A page consists of 64
consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 36-byte user interrupt
vectors area also forms a page. Any FLASH memory page can be erased alone.
Address:
$FE08
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
HVEN
MASS
ERASE
PGM
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)