
Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
150
Freescale Semiconductor
14.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in
Figure 14-3
.
Figure 14-3. SCI Data Formats
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0009
ESCI Prescaler Register
(SCPSC)
See page 170.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PDS2
PDS1
PDS0
PSSB4
PSSB3
PSSB2
PSSB1
PSSB0
0
0
0
0
0
0
0
0
$000A
ESCI Arbiter Control
Register (SCIACTL)
See page 174.
AM1
ALOST
AM0
ACLK
AFIN
ARUN
AROVFL
ARD8
0
0
0
0
0
0
0
0
$000B
ESCI Arbiter Data
Register (SCIADAT)
See page 175.
ARD7
ARD6
ARD5
ARD4
ARD3
ARD2
ARD1
ARD0
0
0
0
0
0
0
0
0
$0013
ESCI Control Register 1
(SCC1)
See page 161.
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
$0014
ESCI Control Register 2
(SCC2)
See page 163.
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
$0015
ESCI Control Register 3
(SCC3)
See page 165.
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
0
$0016
ESCI Status Register 1
(SCS1)
See page 166.
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
0
1
0
0
0
0
0
0
0
0
0
0
0
$0017
ESCI Status Register 2
(SCS2)
See page 168.
BKF
RPF
0
0
0
0
0
0
0
0
$0018
ESCI Data Register
(SCDR)
See page 169.
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
Unaffected by reset
$0019
ESCI Baud Rate Register
(SCBR)
See page 169.
R
LINR
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
R
0
0
0
0
= Unimplemented
= Reserved U = Unaffected
Figure 14-4. ESCI I/O Register Summary
BIT 5
BIT 0
BIT 1
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 2
BIT 3
BIT 4
BIT 6
BIT 7
PARITY
OR DATA
BIT
PARITY
OR DATA
BIT
NEXT
START
BIT
NEXT
START
BIT
STOP
BIT
STOP
BIT
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
START
BIT
START
BIT