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參數(shù)資料
| 型號： | MC80C52XXX-25/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 11/83頁 |
| 文件大?。?/td> | 8336K |
| 代理商： | MC80C52XXX-25/883 |
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156
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
16.8.2 Interrupt Behavior
When an interrupt occurs, an interrupt flag bit is set in the corresponding MOb-CANSTMOB register or in the general CANGIT
register. If in the CANIE register, ENRX / ENTX / ENERR bit are set, then the corresponding MOb bit is set in the CANSITn
register.
To acknowledge a MOb interrupt, the corresponding bits of CANSTMOB register (RXOK, TXOK,...) must be cleared by the
software application. This operation needs a read-modify-write software routine.
To acknowledge a general interrupt, the corresponding bits of CANGIT register (BXOK, BOFFIT,...) must be cleared by the
software application. This operation is made writing a logical one in these interrupt flags (writing a logical zero doesn’t change
the interrupt flag value).
OVRTIM interrupt flag is reset as the other interrupt sources of CANGIT register and is also reset entering in its dedicated
interrupt handler.
When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two
consecutive interrupts can occur, both due to the same error. When a MOb error occurs and is set in its own CANSTMOB
register, no general error is set in CANGIT register.
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| MQ80C52EXXX-25:R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
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| MC80C32-36SHXXX | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32-20:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C52TXXX-16SHXXX:RD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
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