參數(shù)資料
型號: MC8610PX1066JB
廠商: Freescale Semiconductor
文件頁數(shù): 10/96頁
文件大小: 0K
描述: MPU E600 CORE 1066MHZ 783-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.066GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
18
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8610.
Figure 2. Overshoot/Undershoot Voltage for M/B/OVIN
The MPC8610 core voltage must always be provided at nominal VDD_Core (see Table 3 for actual recommended core voltage).
Voltage to the external interface I/Os are provided through separate sets of supply pins and must be provided at the voltages
shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD-based receivers
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced to each externally supplied MVREF signal (nominally set to GVDD/2) as is
appropriate for the (SSTL-18 and SSTL-2) electrical signaling standards.
2.1.3
Output Driver Characteristics
Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output Drive Capability
Driver Type
Programmable
Output Impedance
(
Ω)
Supply
Voltage
Notes
DDR signals
18
36 (half strength mode)
GVDD = 2.5 V
1, 4, 6
DDR2 signals
18
36 (half strength mode)
GVDD = 1.8 V
1, 5, 6
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
G/O/B/X/SVDD + 20%
G/O/B/X/SVDD
G/O/B/X/SVDD + 5%
of tCLK
1
1. tCLK references clocks for various functional blocks as follows:
VIH
VIL
Note:
For DDR, tCLK references MCK.
For LBIU, tCLK references LCLK.
For PCI, tCLK references PCI_CLK or SYSCLK.
For I2C and JTAG, tCLK references SYSCLK.
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