MC68HC908QF4 — Rev. 1.0
Data Sheet
MOTOROLA
External Interrupt (IRQ)
73
Data Sheet — MC68HC908QF4
Section 8. External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and
keyboard interrupt (KBI), provides a maskable interrupt input.
8.2 Features
Features of the IRQ module include the following:
External interrupt pin, IRQ
IRQ interrupt control bits
Hysteresis buffer
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Selectable internal pullup resistor
8.3 Functional Description
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2)
IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the
other shared functionalities. A one enables the IRQ function.
A falling edge on the external interrupt pin can latch a central processor unit (CPU)
interrupt request. Figure 8-2 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch
remains set until one of the following actions occurs:
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
Software clear — Software can clear the interrupt latch by writing to the
acknowledge bit in the interrupt status and control register (INTSCR).
Writing a 1 to the ACK bit clears the IRQ latch.
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered out of reset and is
software-configurable to be either falling-edge or falling-edge and low-level
triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ
pin.
When the interrupt pin is edge-triggered only (MODE = 0), the CPU interrupt
request remains set until a vector fetch, software clear, or reset occurs.
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