Timer Interface Module (TIM)
Data Sheet
MC68HC908QF4 — Rev. 1.0
150
Timer Interface Module (TIM)
MOTOROLA
15.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture
trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIM counter registers matches the
value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF
set and then writing a 0 to CHxF. If another interrupt request occurs before the
clearing sequence is complete, then writing a 0 to CHxF has no effect.
Therefore, an interrupt request cannot be lost due to inadvertent clearing of
CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
Address: $0025
TSC0
Bit 7
654321
Bit 0
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
Address: $0028
TSC1
Bit 7
654321
Bit 0
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
= Unimplemented
Figure 15-8. TIM Channel Status and Control
Registers (TSC0:TSC1)
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Freescale Semiconductor, Inc.
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