Timer Interface Module (TIM)
Data Sheet
MC68HC908QF4 — Rev. 1.0
152
Timer Interface Module (TIM)
MOTOROLA
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the
active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the
channel x output behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O
port, and pin TCHx is available as a general-purpose I/O pin. Table 15-3 shows
how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE:
After initially enabling a TIM channel register for input capture operation and
selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection
flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the
behavior of the channel x output when the TIM counter overflows. When
channel x is an input capture channel, TOVx has no effect. Reset clears the
TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is a 1, setting the CHxMAX bit forces the duty cycle of
buffered and unbuffered PWM signals to 100%. As Figure 15-9 shows, the
CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays
at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Figure 15-9. CHxMAX Latency
OUTPUT
OVERFLOW
TCHx
PERIOD
CHxMAX
OVERFLOW
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
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Freescale Semiconductor, Inc.
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