參數資料
型號: MC92602ZTA
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝: MAPBGA-196
文件頁數: 32/98頁
文件大?。?/td> 896K
代理商: MC92602ZTA
3-8
MC92602 SERDES Reference Manual
MOTOROLA
Functional Description
of drift between receivers. If drift exceeds +6 bit-times the receiver will continue to operate.
However, the received bytes will no longer be synchronized properly because the receiver
remains locked on the initially established synchronization. Word synchronization remains
locked until an event occurs that indicates loss of synchronization.
Word synchronization lock is lost when one or more of the receivers change or lose byte
alignment (byte alignment loss is described in Section 3.3.3.1). Lock is also lost when
overrun/underrun is detected on one or more of the receivers, see Section 3.3.7.1 for more
about overrun/underrun.
Word synchronization lock is lost when explicitly invalidated by asserting DROP_SYNC
and XCVR_x_DISABLE high for at least two clocks (see Section 2.3.4 for details on
performing drop sync). When lock is lost, word synchronization must be re-established
before data ow through the receiver resumes.
The Receiver Interface is disabled during initial word synchronization. No data is produced
at its outputs until word synchronization is achieved and the rst non-idle character is
received. When establishing word synchronization, or when word synchronization is lost,
“Not Word Sync” error is reported as described in Section 3.3.6.3.
3.3.4.1
Recommended Settings for Word Synchronization
Word synchronization can only be used with certain operating modes and has limited
application in others. Table 3-3 describes the relationship between modes and word
synchronization.
Table 3-3. Word Synchronization Settings
Mode
Signals
Recommended
State
Description
Word Synchronization
WSE
High
Enables word synchronization.
Byte Synchronization
BSYNC
High
Word synchronization depends upon Idle character
detection. Byte alignment is required for Idle
detection.
Add/Delete Idle
ADIE
High
When enabled, allows the receiver to add/delete Idle
patterns in order to maintain word synchronization.
This is the recommended operating mode when the
Reference Clock is used to time the receiver interface
(RCCE set low) and there is a frequency offset
between the transmitter and receiver. Idles are added
or dropped to maintain word alignment.
ICompatibility Mode
COMPAT
Low
Word synchronization is not supported in compatibility
mode.
Ten-Bit Interface
TBIE
n/a
When enabled, the Idle character must be part of the
TBI code set.
When disabled, the Idle is naturally supported by the
8B/10B codes.
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