Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ128 Series Data Sheet, Rev. 1
254
Freescale Semiconductor
Figure 12-1. MC9S08DZ128 Block Diagram with MSCAN Highlighted
ANALOG COMPARATOR
(ACMP1)
ACMP1O
ACMP1-
ACMP1+
VSS
VDD
IIC MODULE (IIC1)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
USER MEMORY
MC9S08DZ128 = 128K_2K_8K
HCS08 CORE
CPU
BDC
6-CHANNEL TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
VOLTAGE
REGULATOR
COP
IRQ
LVD
OSCILLATOR
MULTI-PURPOSE
CLOCK
RESET
VREFL
VREFH
ANALOG-TO-DIGITAL
CONVERTER (ADC)
24-CHANNEL,12-BIT
BKGD/MS
INTERFACE (SCI1)
SERIAL COMMUNICATIONS
SDA1
SCL1
MISO1
SS1
SPSCK1
TxD1
RxD1
XTAL
EXTAL
8
2-CHANNEL TIMER/PWM
MODULE (TPM2)
REAL-TIME COUNTER (RTC)
DEBUG MODULE (DBG)
IRQ
PTA3/PIA3/ADP3/ACMP1O
PTA4/PIA4/ADP4
PTA5/PIA5/ADP5
PTA2/PIA2/ADP2/ACMP1-
PTA1/PIA1/ADP1/ACMP1+
PTA0/PIA0/ADP0/MCLK
POR
T
A
PTA6/PIA6/ADP6
PTA7/PIA7/ADP7/IRQ
MOSI1
PTB3/PIB3/ADP11
PTB4/PIB4/ADP12
PTB5/PIB5/ADP13
PTB2/PIB2/ADP10
PTB1/PIB1/ADP9
PTB0/PIB0/ADP8
POR
T
B
PTB6/PIB6/ADP14
PTB7/PIB7/ADP15
PTC3/ADP19
PTC4/ADP20
PTC5/ADP21
PTC2/ADP18
PTC1/ADP17
PTC0/ADP16
POR
T
C
PTC6/ADP22
PTC7/ADP23
PTD3/PID3/TPM1CH1
PTD4/PID4/TPM1CH2
PTD5/PID5/TPM1CH3
PTD2/PID2/TPM1CH0
PTD1/PID1/TPM2CH1
PTD0/PID0/TPM2CH0
POR
T
D
PTD6/PID6/TPM1CH4
PTD7/PID7/TPM1CH5
PTE3/SPSCK1
PTE4/SCL1/MOSI1
PTE5/SDA1/MISO1
PTE2/SS1
PTE1/RxD1
PTE0/TxD1
POR
T
E
PTE6/TxD2/TXCAN
PTE7/RxD2/RXCAN
PTF3/TPM2CLK/SDA1
PTF4/ACMP2+
PTF5/ACMP2-
PTF2/TPM1CLK/SCL1
PTF1/RxD2
PTF0/TxD2
POR
T
F
PTF6/ACMP2O
PTF7
PTG1/XTAL
PTG2
PTG3
POR
T
G
PTG4
PTG5
PTG0/EXTAL
VSSA
VDDA
BKP
INT
ANALOG COMPARATOR
(ACMP2)
ACMP2O
ACMP2-
ACMP2+
INTERFACE (SCI2)
SERIAL COMMUNICATIONS
TxD2
RxD2
NETWORK (MSCAN)
CONTROLLER AREA
TXCAN
RxCAN
ADP7-ADP0
ADP15-ADP8
ADP23-ADP16
6
TPM1CH5 -
TPM2CH1,
TPM2CH0
TPM2CLK
TPM1CLK
TPM1CH0
PTG6/SCL2
PTG7/SDA2
FLASH _EEPROM _RAM
MC9S08DZ96 = 96K_2K_6K
MC9S08DV128 = 128K_0K_6K
MC9S08DV96 = 96K_0K_4K
PTH3/MISO2
PTH4
PTH5
PTH2/MOSI2
PTH1/SPSCK2
PTH0/SS2
POR
T
H
PTH6
PTH7
PTJ3/PIJ3/TMP3CH3
PTJ4/PIJ4
PTJ5/PIJ5
PTJ2/PIJ2/TPM3CH2
PTJ1/PIJ1/TPM3CH1
PTJ0/PIJ0/TMP3CH0
POR
T
J
PTJ6/PIJ6
PTJ7/PIJ7/TPM3CLK
PTK3
PTK4
PTK5
PTK2
PTK1
PTK0
POR
T
K
PTK6
PTK7
PTL3
PTL4
PTL5
PTL2
PTL1
PTL0
POR
T
L
PTL6
PTL7
IIC MODULE (IIC2)
SDA2
SCL2
4-CHANNEL TIMER/PWM
MODULE (TPM3)
4
TPM3CH3
TPM3CLK
TPM3CH0 -
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
MISO2
SS2
SPSCK2
MOSI2
(XOSC)
GENERATOR
(MCG)
●
- In 48-pin package, VDDA and VREFH are internally connected to each other and VSSA and VREFL are internally connected to each other.
- Pin not connected in 64-pin and 48-pin packages
● - Pin not available in the 48-pin package
●