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鍨嬭櫉锛� MCF5208CVM166
寤犲晢锛� Freescale Semiconductor
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绯诲垪锛� MCF520x
鏍稿績铏曠悊鍣細 Coldfire V2
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RAM 瀹归噺锛� 16K x 8
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灏佽/澶栨锛� 196-LBGA
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Electrical Characteristics
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
25
5.7
External Interface Timing Characteristics
Table 11 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.
9
XTAL Current
IXTAL
13
mA
10
Total on-chip stray capacitance on XTAL
CS_XTAL
1.5
pF
11
Total on-chip stray capacitance on EXTAL
CS_EXTAL
1.5
pF
12
Crystal capacitive load
CL
See crystal
spec
13
Discrete load capacitance for XTAL
CL_XTAL
2*CL -
CS_XTAL -
CPCB_XTAL
7
pF
14
Discrete load capacitance for EXTAL
CL_EXTAL
2*CL -
CS_EXTAL -
CPCB_EXTAL
pF
17
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
鈥�
10
TBD
% fsys/2
18
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
0.8
2.2
%fsys/2
19
VCO Frequency. fvco = (fref * PFD)/4
fvco
350
540
MHz
NOTES:
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24 MHz. For higher input clock
frequencies, the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2
All internal registers retain data at 0 Hz.
3
This parameter is guaranteed by characterization before qualification rather than 100% tested.
4
Proper PC board layout procedures must be followed to achieve specifications.
5
This parameter is guaranteed by design rather than 100% tested.
6
This specification is the PLL lock time only and does not include oscillator start-up time.
7
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10
渭s, or equivalently the modulation rate is 100KHz.
11 Modulation range determined by hardware design.
Table 10. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
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