MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3 Fr" />
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鍨嬭櫉(h脿o)锛� MCF5208CVM166
寤犲晢锛� Freescale Semiconductor
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绯诲垪锛� MCF520x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 166.67MHz
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宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 196-LBGA
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Electrical Characteristics
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
31
5.8.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.
Table 13. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
鈥�
Frequency of Operation
鈥�
60
83.33
Mhz
1
NOTES:
1
The frequency of operation is 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the same
frequency as the internal bus clock.
DD1
Clock Period (SD_CLK)
tDDCK
12
16.67
ns
2
SD_CLK is one SDRAM clock in (ns).
DD2
Pulse Width High
tDDCKH
0.45
0.55
SD_CLK
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
DD3
Pulse Width Low
tDDCKL
0.45
0.55
SD_CLK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
tSDCHACV
鈥�0.5
脳 SD_CLK
+1.0
ns
4
4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature, and
voltage variations.
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
鈥�
ns
鈥�
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
1.25
SD_CLK
鈥�
DD7
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
tDQDMV
1.5
鈥�
ns
5
6
5
This specification relates to the required input setup time of today鈥檚 DDR memories. The device鈥檚 output setup should be larger
than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
6
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
DD8
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tDQDMI
1.0
鈥�
ns
7
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
鈥�1
ns
8
DD10
Input Data Hold Relative to DQS.
tDIDQ
0.25
脳 SD_CLK
+0.5ns
鈥攏s
9
DD11
DQS falling edge from SDCLK rising (output hold time)
tDQLSDCH
0.5
鈥�
ns
鈥�
DD12
DQS input read preamble width (tRPRE)tDQRPRE
0.9
1.1
SD_CLK
鈥�
DD13
DQS input read postamble width (tRPST)tDQRPST
0.4
0.6
SD_CLK
鈥�
DD14
DQS output write preamble width (tWPRE)tDQWPRE
0.25
鈥�
SD_CLK
鈥�
DD15
DQS output write postamble width (tWPST)tDQWPST
0.4
0.6
SD_CLK
鈥�
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MCF5208EC 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ColdFire銏� Microprocessor
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