MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3 Fr" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCF5208CVM166
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 20/46闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32-BIT 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 126
绯诲垪锛� MCF520x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 166.67MHz
閫ｉ€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 50
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 16K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.4 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 鎵樼洡
Electrical Characteristics
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
27
5.7.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
Table 11. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
83.33
Mhz
fsys/2
FB1
Clock Period (FB_CLK)
tFBCK
12
ns
tcyc
FB2
Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
tFBCHDCV
鈥�7.0
ns
1
NOTES:
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8, 鈥淪DRAM Bus鈥� for SD_CS[1:0]
timing.
FB3
Data, and Control Output Hold ((A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
tFBCHDCI
1鈥�
ns
2
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for
more information.
FB4
Data Input Setup
tDVFBCH
3.5
鈥�
ns
FB5
Data Input Hold
tDIFBCH
0鈥�
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4鈥�
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0鈥�
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
MC9328MXLVP20 IC MCU I.MX 200MHZ 225-MAPBGA
MC9328MXLDVP20 IC MCU I.MX 200MHZ 225-MAPBGA
MCF52277CVM160 IC MCU 32BIT 166.67MHZ 196MAPBGA
MCIMX27LVOP4A IC LOW END I.MX27 404-MAPBGA
MCIMX27LMOP4A IC MPU I.MX27 IN 19X19 473MAPBGA
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
MCF5208CVM166J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU ColdFire Micro-Proc RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5208EC 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:ColdFire銏� Microprocessor
MCF5208EC_08 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:MCF5208 ColdFire? Microprocessor Data Sheet
MCF52100CAE66 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU KIRIN0 WITHOUT USB RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF52100CAE80 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU KIRIN0 WITHOUT USB RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�(h脿o)锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩笺€備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

*
*
*
    • 鎴�
    • 閲囪喘
    • 鎼滅储
    • 浼氬憳