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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCF5272VM66R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 137/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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Ethernet Module
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
Freescale Semiconductor
11-3
The descriptor controller opens and closes the buffer descriptors. The DMA controller manages the data
transfer. As soon as the DMA channel is initialized, it begins transferring data. An on-board RAM acts as
both a transmit and receive FIFO, and also provides scratch memory for the FEC.
The RAM is the focal point of all data flow in the FEC. The RAM is divided into three sections: transmit
FIFO, receive FIFO, and descriptor controller memory. User data flows to or from the DMA unit from or
to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block. Receive
data flows from the receive block into the receive FIFO.
The user controls the FEC by writing into control registers located in each block. The control and status
registers (CSRs) provide global control (for example, Ethernet reset and enable) and interrupt handling.
The MII block provides a serial channel for the FEC and external physical layer device to pass control and
status information.
The descriptor controller manages data flow in both transmit and receive directions. It is programmed with
microcode to open and close buffer descriptors, control the transmit collision recovery process, and filter
received frame addresses.
The descriptor controller accesses both the transmit and receive descriptor rings through the descriptor
access block. The descriptor access block acts as a dedicated single channel DMA that either reads a
descriptor in external user memory or writes an updated descriptor back into user memory.
11.3
Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by RCR[MII_MODE]. In MII mode, the 802.3 standard
defines and the FEC module supports 18 signals. These are shown in Table 11-1.
Table 11-1. MII Mode
Signal Description
MCF5272 Pin
Transmit clock
E_TxCLK
Transmit enable
E_TxEN
Transmit data
E_TxD[3:0]
Transmit error
E_TxER
Collision
E_COL
Carrier sense
E_CRS
Receive clock
E_RxCLK
Receive enable
E_RxDV
Receive data
E_RxD[3:0]
Receive error
E_RxER
Management channel clock
E_MDC
Management channel serial data
E_MDIO
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-21F-CU-S CONVERTER MOD DC/DC 72V 200W
VI-21D-CU-S CONVERTER MOD DC/DC 85V 200W
VI-21B-CU-S CONVERTER MOD DC/DC 95V 200W
VI-214-CU-S CONVERTER MOD DC/DC 48V 200W
JBXER0G04FCSDSR CONN RCPT 4POS FRONT MNT CRIMP
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MCF5272VM66R2 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microcontroler
MCF5272VM66R2J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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