MCF5272 ColdFire Integrated Microprocessor U" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5272VM66R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 227/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯欐簴鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
13-6
Freescale Semiconductor
.
Figure 13-6. B-Channel Unencoded and HDLC Encoded Data
13.2.3.2
B-Channel HDLC Encoded Data
When the incoming B channels contain HDLC encoded data they are presented on the physical line least
significant bit (lsb) first. The Soft HDLC expects the first bit received to be aligned in the lsb position of
a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb (least significant bit) first
for B1 and B2 the lsb is right-aligned in the transmit and receive shift register, that is, the first bit of the
B-channel received is aligned in the lsb position through to the last received bit of a byte that is aligned in
the msb position.
The ordering of the bytes over four frames within the longword register is as for unencoded data; that is,
the first frame is aligned in the MSB through to the fourth frame, which is aligned in the LSB position. See
13.2.3.3
D-Channel HDLC Encoded Data
When the incoming D channels contain HDLC-encoded data, they are presented on the physical line lsb
first. The Soft HDLC expects the first bit received to be aligned in the lsb position of a byte, with the last
bit received aligned in the msb position.
DCL
FSR
Din/Dout
Frame 0
Frame 1
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR
Frame 0
Frame 1
Frame 2
Frame 3
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2
D0 D1
Din/Dout
B 1
B 2
D
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5
D0 D1
B0 B1 B2 B3 B4 B5 B6 B7
Unencoded
HDLC
Encoded
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-21F-CU-S CONVERTER MOD DC/DC 72V 200W
VI-21D-CU-S CONVERTER MOD DC/DC 85V 200W
VI-21B-CU-S CONVERTER MOD DC/DC 95V 200W
VI-214-CU-S CONVERTER MOD DC/DC 48V 200W
JBXER0G04FCSDSR CONN RCPT 4POS FRONT MNT CRIMP
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鍙冩暩(sh霉)鎻忚堪
MCF5272VM66R2 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microcontroler
MCF5272VM66R2J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
MCF5274CVM166 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5275 V2CORE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MCF5274CVM166J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:MCF5275 V2CORE - Bulk
MCF5274LCVM166 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5275 V2CORE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324