MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3 F" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCF5272VM66R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 61/544闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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�(y猫)绗�465闋�(y猫)绗�466闋�(y猫)绗�467闋�(y猫)绗�468闋�(y猫)绗�469闋�(y猫)绗�470闋�(y猫)绗�471闋�(y猫)绗�472闋�(y猫)绗�473闋�(y猫)绗�474闋�(y猫)绗�475闋�(y猫)绗�476闋�(y猫)绗�477闋�(y猫)绗�478闋�(y猫)绗�479闋�(y猫)绗�480闋�(y猫)绗�481闋�(y猫)绗�482闋�(y猫)绗�483闋�(y猫)绗�484闋�(y猫)绗�485闋�(y猫)绗�486闋�(y猫)绗�487闋�(y猫)绗�488闋�(y猫)绗�489闋�(y猫)绗�490闋�(y猫)绗�491闋�(y猫)绗�492闋�(y猫)绗�493闋�(y猫)绗�494闋�(y猫)绗�495闋�(y猫)绗�496闋�(y猫)绗�497闋�(y猫)绗�498闋�(y猫)绗�499闋�(y猫)绗�500闋�(y猫)绗�501闋�(y猫)绗�502闋�(y猫)绗�503闋�(y猫)绗�504闋�(y猫)绗�505闋�(y猫)绗�506闋�(y猫)绗�507闋�(y猫)绗�508闋�(y猫)绗�509闋�(y猫)绗�510闋�(y猫)绗�511闋�(y猫)绗�512闋�(y猫)绗�513闋�(y猫)绗�514闋�(y猫)绗�515闋�(y猫)绗�516闋�(y猫)绗�517闋�(y猫)绗�518闋�(y猫)绗�519闋�(y猫)绗�520闋�(y猫)绗�521闋�(y猫)绗�522闋�(y猫)绗�523闋�(y猫)绗�524闋�(y猫)绗�525闋�(y猫)绗�526闋�(y猫)绗�527闋�(y猫)绗�528闋�(y猫)绗�529闋�(y猫)绗�530闋�(y猫)绗�531闋�(y猫)绗�532闋�(y猫)绗�533闋�(y猫)绗�534闋�(y猫)绗�535闋�(y猫)绗�536闋�(y猫)绗�537闋�(y猫)绗�538闋�(y猫)绗�539闋�(y猫)绗�540闋�(y猫)绗�541闋�(y猫)绗�542闋�(y猫)绗�543闋�(y猫)绗�544闋�(y猫)
Debug Support
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
Freescale Semiconductor
5-35
Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All
interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use
supervisor instructions to save the necessary context such as the state of all program-visible registers into
a reserved memory area.
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
If a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt service routine,
another debug interrupt is generated after the completion of the RTE instruction.
5.6.1.1
Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three
different ways:
Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See Section 5.5.1, 鈥淐PU Halt.鈥�
A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
All interrupts are ignored, including level-7 interrupts.
If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.
This includes stack frame writes and the vector fetch for the exception that forced entry into this
mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
5.6.2
Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except those following operations that access
processor/memory registers:
Read/write address and data registers
Read/write control registers
For BDM commands that access memory, the debug module requests the processor鈥檚 local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
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VI-21D-CU-S CONVERTER MOD DC/DC 85V 200W
VI-21B-CU-S CONVERTER MOD DC/DC 95V 200W
VI-214-CU-S CONVERTER MOD DC/DC 48V 200W
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