參數(shù)資料
型號: MCIMX258CVM4
廠商: Freescale Semiconductor
文件頁數(shù): 105/153頁
文件大?。?/td> 0K
描述: IC MPU I.MX25 IND 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
55
3.7.6
External Memory Interface (EMI) Timing
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash
controller (NFC), and wireless external interface module (WEIM). The following subsections give timing
information for these submodules.
Table 43. CSPI Interface Timing Parameters
ID
Parameter Description
Symbol
Minimum
Maximum
Units
t1
CSPI master SCLK cycle time
tclko
60.2
ns
t2
CSPI master SCLK high time
tclkoH
22.65
ns
t3
CSPI master SCLK low time
tclkoL
22.47
ns
t1’
CSPI slave SCLK cycle time
tclki
60.2
ns
t2’
CSPI slave SCLK high time
tclkiH
30.1
ns
t3’
CSPI slave SCLK low time
tclkiL
30.1
ns
t4
CSPI SCLK transition time
tpr
1
1 The output SCLK transition time is tested with 25 pF drive.
2.6
8.5
ns
t5
SS
n output pulse width
tWsso
2Tsclk
2 +T
wait
3
2 T
sclk = CSPI clock period
3 T
wait = Wait time, as specified in the sample period control register
——
t5’
SS
n input pulse width
tWssi
Tper
4
4 T
per = CSPI reference baud rate clock period (PERCLK2)
——
t6
SS
n output asserted to first SCLK edge (SS output setup
time)
tSsso
3Tsclk
——
t6’
SS
n input asserted to first SCLK edge (SS input setup
time)
tSssi
Tper
——
t7
CSPI master: Last SCLK edge to SS
n negated (SS
output hold time)
tHsso
2Tsclk
——
t7’
CSPI slave: Last SCLK edge to SS
n negated (SS input
hold time)
tHssi
30
ns
t8
CSPI master: CSPI1_RDY low to SS
n asserted
(CSPI1_RDY setup time)
tSrdy
2Tper
5Tper
t9
CSPI master: SS
n negated to CSPI1_RDY low
tHrdy
0—
ns
t10
Output data setup time
tSdatao
(tclkoL or tclkoH or
tclkiL or tclkiH) –
Tipg
5
5 T
ipg = CSPI main clock IPG_CLOCK period
——
t11
Output data hold time
tHdatao
tclkoL or tclkoH or
tclkiL or tclkiH
——
t12
Input data setup time
tSdatai
Tipg + 0.5
ns
t13
Input data hold time
tHdatai
0—
ns
t14
Pause between data word
tpause
0—
ns
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