參數(shù)資料
型號： MCIMX258CVM4
廠商： Freescale Semiconductor
文件頁數(shù)： 138/153頁
文件大?。?/td> 0K
描述： IC MPU I.MX25 IND 400MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： i.MX25
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 128
程序存儲器類型： 外部程序存儲器
RAM 容量： 144K x 8
電壓 - 電源 (Vcc/Vdd)： 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 400-LFBGA
包裝： 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
85
3.7.9
Fast Ethernet Controller (FEC) Timing
The FEC is designed to support both 10- and 100-Mbps Ethernet networks compliant with the IEEE 802.3
standard. An external transceiver interface and transceiver function are required to complete the interface
to the media. The FEC supports 10/100 Mbps MII (18 pins altogether), 10/100 Mbps RMII (ten pins,
including serial management interface) and the 10-Mbps-only 7-Wire interface (which uses seven of the
MII pins), for connection to an external Ethernet transceiver. All signals are compatible with transceivers
operating at a voltage of 3.3 V.
The following subsections describe the timing for MII and RMII modes.
3.7.9.1
FEC MII Mode Timing
The following subsections describe MII receive, transmit, asynchronous inputs, and serial management
signal timings.
3.7.9.1.4
MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK)
The receiver functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 55 shows MII receive signal timings. Table 62 describes the timing parameters (M1–M4) shown in
the figure.
Figure 55. MII Receive Signal Timing Diagram
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
Table 62. MII Receive Signal Timing
ID
Characteristic1
Min.
Max.
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2
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