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| 型號： | MCP4728-E/UN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/I2C 10-MSOP |
| 視頻文件： | MCP4728 Evaluation Board Demo |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 673 (CN2011-ZH PDF) |
| 配用： | MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728 |
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2010 Microchip Technology Inc.
DS22187E-page 21
MCP4728
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1
Supply Voltage Pins (VDD, VSS)
VDD is the power supply pin for the device. The voltage
at the VDD pin is used as a power supply input as well
as a DAC external reference. The power supply at the
VDD pin should be as clean as possible for a good DAC
performance.
It is recommended to use an appropriate bypass
capacitor of about 0.1 F (ceramic) to ground. An
additional 10 F capacitor (tantalum) in parallel is also
recommended to further attenuate high-frequency
noise present in application boards. The supply voltage
(VDD) must be maintained in the 2.7V to 5.5V range for
specified operation.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low-impedance connection. If an
analog ground path is available in the application
printed circuit board (PCB), it is highly recommended
that the VSS pin be tied to the analog ground path, or
isolated within an analog ground plane of the circuit
board.
3.2
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
MCP4728 device acts only as a slave and the SCL pin
accepts only external input serial clocks. The input data
from the Master device is shifted into the SDA pin on
the rising edges of the SCL clock, and output from the
MCP4728 occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin.
Refer
to
Interface communication.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 k
Ω to 10 kΩ for Standard (100 kHz) and
Fast (400 kHz) modes, and less than 1 k
Ω for High
Speed mode (3.4 MHz).
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
Name
Pin Type
Function
1
VDD
P
Supply Voltage
2SCL
OI
I2C Serial Clock Input
3
SDA
OI/OO
I2C Serial Data Input and Output
4LDAC
ST
This pin is used for two purposes:
(a) Synchronization Input. It is used to transfer the contents of the DAC input
registers to the output registers (VOUT).
(b) Select the device for reading and writing I2C address bits.
5
RDY/BSY
OO
This pin is a status indicator of EEPROM programming activity. An external pull-up
resistor (about 100 k
Ω) is needed from RDY/BSY pin to V
DD line. (Note 1)
6VOUT A
AO
Buffered analog voltage output of channel A. The output amplifier has rail-to-rail
operation.
7VOUT B
AO
Buffered analog voltage output of channel B. The output amplifier has rail-to-rail
operation.
8VOUT C
AO
Buffered analog voltage output of channel C. The output amplifier has rail-to-rail
operation.
9VOUT D
AO
Buffered analog voltage output of channel D. The output amplifier has rail-to-rail
operation.
10
VSS
P
Ground reference.
Legend: P = Power, OI = Open-Drain Input, OO = Open-Drain Output, ST = Schmitt Trigger Input Buffer,
AO = Analog Output
Note 1:
This pin needs an external pull-up resistor from VDD line. Leave this pin float if it is not used.
2:
This pin can be driven by MCU.
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