參數(shù)資料
型號(hào)： MCP4728-E/UN
廠商： Microchip Technology
文件頁(yè)數(shù)： 30/33頁(yè)
文件大小： 0K
描述： IC DAC 12BIT W/I2C 10-MSOP
視頻文件： MCP4728 Evaluation Board Demo
標(biāo)準(zhǔn)包裝： 100
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 673 (CN2011-ZH PDF)
配用： MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728
MCP4728
DS22187E-page 6
2010 Microchip Technology Inc.
Dynamic Performance (Note 4)
Major Code Transition
Glitch
—
45
—
nV-s
1 LSB code change around major
carry (from 7FFh to 800h)
Digital Feedthrough
—
<10
—
nV-s
Analog Crosstalk
—
<10
—
nV-s
DAC-to-DAC Crosstalk
—
<10
—
nV-s
Digital Interface
Output Low Voltage
VOL
—
0.4
V
IOL =3 mA
SDA and RDY/BSY pins
Schmitt Trigger
Low Input
Threshold Voltage
VIL
——
0.3VDD
V
VDD >2.7V.
SDA, SCL, LDAC pins
——
0.2VDD
V
VDD ≤ 2.7V.
SDA, SCL, LDAC pins
Schmitt Trigger
High Input
Threshold Voltage
VIH
0.7VDD
—
V
SDA, SCL, LDAC pins
Input Leakage
ILI
—
±1
A
SCL = SDA = LDAC =VDD,
SCL = SDA = LDAC =VSS
Pin Capacitance
CPIN
—
3
pF
EEPROM
EEPROM Write Time
TWRITE
—
25
50
ms
EEPROM write time
Data Retention
—
200
—
Years
At +25°C,
LDAC Input
LDAC Low Time
TLDAC
210
—
ns
Updates analog outputs
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at V
DD = +2.7V to 5.5V, VSS =0V,
RL =5 kΩ, CL = 100 pF, GX =1, TA = -40°C to +125°C. Typical values are at +25°C, VIH =VDD, VIL =VSS.
Parameter
Symbol
Min
Typical
Max
Units
Conditions
Note 1:
All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000.
2:
The power-up ramp rate measures the rise of VDD over time.
3:
This parameter is ensured by design and not 100% tested.
4:
This parameter is ensured by characterization and not 100% tested.
5:
Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V.
6:
Time delay to settle to a new reference when switching from external to internal reference or vice versa.
7:
This parameter is indirectly tested by Offset and Gain error testing.
8:
Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.
9:
This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT.
This time delay is not included in the output settling time specification.
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