參數(shù)資料
型號(hào): MCP4728-E/UN
廠商: Microchip Technology
文件頁(yè)數(shù): 33/33頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT W/I2C 10-MSOP
視頻文件: MCP4728 Evaluation Board Demo
標(biāo)準(zhǔn)包裝: 100
設(shè)置時(shí)間: 6µs
位數(shù): 12
數(shù)據(jù)接口: EEPROM,I²C,串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 673 (CN2011-ZH PDF)
配用: MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728
2010 Microchip Technology Inc.
DS22187E-page 9
MCP4728
SCL Rise Time
TRSCL
1000
ns
Standard Mode
20 + 0.1Cb
300
ns
Fast Mode
20
80
ns
High Speed Mode 1.7
20
160
ns
High Speed Mode 1.7
10
40
ns
High Speed Mode 3.4
10
80
ns
High Speed Mode 3.4
SDA Rise Time
TRSDA
1000
ns
Standard Mode
20 + 0.1Cb
300
ns
Fast Mode
20
80
ns
High Speed Mode 1.7
10
40
ns
High Speed Mode 3.4
SCL Fall Time
TFSCL
300
ns
Standard Mode
20 + 0.1Cb
300
ns
Fast Mode
20
80
ns
High Speed Mode 1.7
10
40
ns
High Speed Mode 3.4
SDA Fall Time
TFSDA
300
ns
Standard Mode
20 + 0.1Cb
300
ns
Fast Mode
20
160
ns
High Speed Mode 1.7
10
80
ns
High Speed Mode 3.4
Data Input Setup Time
TSU:DAT
250
ns
Standard Mode
100
ns
Fast Mode
10
ns
High Speed Mode 1.7
10
ns
High Speed Mode 3.4
Data Hold Time
(Input, Output)
THD:DAT
0
3450
ns
Standard Mode
0
900
ns
Fast Mode
0
150
ns
High Speed Mode 1.7
0
70
ns
High Speed Mode 3.4
Output Valid from Clock
TAA
0
3750
ns
Standard Mode
0
1200
ns
Fast Mode
0
310
ns
High Speed Mode 1.7
0
150
ns
High Speed Mode 3.4
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for T
A = -40 to +125°C, VSS = 0V,
Standard and Fast Mode: VDD = +2.7V to +5.5V
High Speed Mode: VDD = +4.5V to +5.5V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is ensured by characterization and is not 100% tested.
2:
After a Repeated Start condition or an Acknowledge bit.
3:
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If
this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
Data Input: This parameter must be longer than t
SP.
Data Output: This parameter is characterized, and tested indirectly by testing T
AA parameter.
4:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA).
5:
Time between Start and Stop conditions.
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