This command is used to read the I
參數(shù)資料
型號(hào)： MCP4728-E/UN
廠商： Microchip Technology
文件頁(yè)數(shù)： 27/33頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT W/I2C 10-MSOP
視頻文件： MCP4728 Evaluation Board Demo
標(biāo)準(zhǔn)包裝： 100
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： EEPROM，I²C，串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 673 (CN2011-ZH PDF)
配用： MCP4728EV-ND - BOARD EVAL 12BIT 4CH DAC MCP4728
2010 Microchip Technology Inc.
DS22187E-page 33
MCP4728
5.4.4
GENERAL CALL READ ADDRESS
BITS
This command is used to read the I2C address bits of
the device. If the second byte is “00001100” (0Ch), the
device will output its address bits stored in EEPROM
and register. This command uses the LDAC pin to
select the device of interest to read on the I2C bus. The
LDAC pin needs a logic transition from “High” to “Low”
during the negative pulse of the 8th clock of the second
byte, and stays “Low” until the end of the 3rd byte. The
maximum clock rate for this command is 400 kHz.
FIGURE 5-6:
General Call Read I2C Address.
ACK
(MCP4728)
Restart
(General Call Address)
1st Byte
2nd Byte
Address Bits
in
Address Bits
in Input
Note 3
(Notes 1, 2, 3)
LDAC Pin
4th Byte
ACK (Master)
Start
3rd Byte
Note 3
ACK Clock
Clock Pulse
LDAC Pin
2nd Byte
3rd Byte
4th Byte
Note 2 (a)
ACK Clock
Note 2(b)
Stay “Low” until the end of the 3rd Byte
Note 2(b, c)
Restart Clock
(CLK Line)
Reading Address Bits
Stop
6
7
8
9
Sr
1
2
3
4
5
6
7
8
9
1
2
3
Note 1: Clock Pulse and LDAC Transition Details.
2:
LDAC pin events at the 2nd and 3rd bytes.
a.
Keep LDAC pin “High” until the end of the positive pulse of the 8th clock of the 2nd byte.
b.
LDAC pin makes a transition from “High” to “Low” during the negative pulse of the 8th clock of the 2nd
byte (just before the rising edge of the 9th clock) and stays “Low” until the rising edge of clock 9 of the
3rd byte.
c.
The MCP4728 device does not acknowledge the 3rd byte if the conditions (a) and (b) are not met.
3: LDAC pin resumes its normal function after “Stop” bit.
S 00000000 A 0 0001100 A Sr 1 100 X X X 1 A A2A1A0 1 A2A1A0 0 A P
Restart Byte
EEPROM
Register
Clock and LDAC Transition Details:
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