參數(shù)資料
型號(hào)： MCZ33991EG
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Gauge Driver Integrated Circuit
中文描述： 儀表驅(qū)動(dòng)集成電路
文件頁數(shù)： 14/36頁
文件大?。?/td> 481K
代理商： MCZ33991EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
33991
TIMING DESCRIPTIONS AND DIAGRAMS
COMMUNICATION MEMORY MAPS
MODULE MEMORY MAP
Various registers of the 33991 SPI module are addressed
by the three MSB of the 16-bit word received serially.
Functions to be controlled include:
Individual gauge drive enabling
Power-up/down
Internal clock calibration
Gauge pointer position and velocity
Gauge pointer zeroing
Status reporting includes:
Individual gauge over temperature condition
Battery out of range condition
Internal clock status
Confirmation of coil output changes should result in pointer
movement
Table 2 provides the register available to control the above functions.
REGISTER DESCRIPTIONS
Power, Enable, and Calibration Register (PECR)
This register allows the master to independently enable or
disable the output drivers of the two gauge controllers.
SI address 000 (Power, Enable, & Calibration Register is
illustrated in Figure 3. A write to the 33991 using this register
allows the master to independently enable or disable the
output drivers of the two gauge controllers as well as to
calibrate the internal clock, or send a null command for the
purpose of reading the status bits. This register is also used
to place the 33991 into a low current consumption mode.
Each of the gauge drivers can be enabled by writing a logic
[1] to their assigned address bits, D0 and D1 respectively.
This feature could be useful to disable a driver if it is failing or
not being used. The device can be placed into a standby
current mode by writing a logic[0] to both D0 and D1. During
this state, most current consuming circuits are biased off.
When in the Standby mode, the internal clock will remain ON.
The internal state machine utilizes a ROM table of step
times defining the duration the motor will spend at each
microstep as it accelerates or decelerates to a commanded
position. The accuracy of the acceleration and velocity of the
motor is directly related to the accuracy of the internal clock.
Although the accuracy of the internal clock is temperature
independent, the non-calibrated tolerance is +70 to -35
percent. The 33991 was designed with a feature allowing
the internal clock to be software calibrated to a tighter
tolerance of ±10 percent, using the CS pin and a reference
time pulse provided by the micro controller.
Calibration of the internal clock is initiated by writing a logic
[1] to D3. The calibration pulse must be 8
μ
s for an internal
clock speed of 1MHz, will be sent on the CS pin immediately
after the SPI word is sent. No other SPI lines will be toggled.
A clock calibration will be allowed only if the gauges are
disabled or the pointers are not moving, as indicated by
status bits ST4 and ST5.
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires the nominal internal clock frequency fall
below 1MHz. The frequency range of the calibrated clock will
always be below 1MHz if bit D4 is logic [0] when initiating a
calibration command, followed by an 8
μ
s reference pulse.
The frequency will be centered at 1MHz if bit D4 is logic [1].
Some applications may require a slower calibrated clock
due to a lower motor gear reduction ratio. Writing a logic [1]
to bit D2 will slow the internal oscillator by one-third, leading
to a situation where it is possible to calibrate at maximum 667
kHz or centered at 667 kHz. In these cases, it may be
necessary to provide a longer calibration pulse of exactly 12
μ
s, without any indication of a calibration fault at status bit
ST7, as should be the case for 1 MHz if D2 is left logic [0].
If bit D12 is logic [1] during a PECR command, the state of
D11: D0 will be ignored; this is referenced as the null
command and can be used to read device status without
affecting device operation.
These bits are
write-only
.
PE12—Null Command for Status Read
0 = Disable
1 = Enable
PE11: PE5 These bits must be transmitted as logic [0] for
valid PECR commands.
PE4—Clock Calibration Frequency Selector
0 = Maximum f=1MHz (for 8us calibration pulse)
Table 5. Module Memory Map
Address [15:13]
Use
Name
000
Power, Enable, and Calibration
Register
PECR
001
Maximum Velocity Register
VELR
010
Gauge 0 Position Register
POS0R
011
Gauge 1 Position Register
POS1R
100
Return to 0 Register
RTZR
101
Return to 0 Confirmation Register
RTZCR
110
Not Used
111
Reserved for Test
Table 6. Power, Enable and Calibration Register (PECR)
Address: 000
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Write
PE12
0
0
0
0
0
0
0
PE4
PE3
PE2
PE1
PE0
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